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發表於 2008-4-9 19:56:37
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原來是floating的問題
6 P O8 I0 J' Q H0 N了解了
$ q3 L; z8 g; k8 Q3 H! j感謝你的解答 
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另外還有一個問題 也是在DV階段跑出來的warning 如下:( `7 k7 p* L, o& k
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design_vision-xg-t> write_sdf -version 1.0 dpwm2.sdf
7 |4 n$ `7 B2 l9 o" o& n3 F+ |Information: Annotated 'cell' delays are assumed to include load delay. (UID-282)
K6 z/ X- F! ^" b+ f: h$ MInformation: Writing timing information to file '/export/home/stevetu/batman/dpwm2/dpwm2.sdf'. (WT-3)
' {$ s0 _- L# a: Q6 w" GWarning: Disabling timing arc between pins 'CDN' and 'Q' on cell 'mp_dpwm1/DFF_reg[102]'4 b4 T i- z0 }" S/ k) ^/ L5 m# M
to break a timing loop. (OPT-314)5 S* K3 t- g( r4 H. c
Warning: Disabling timing arc between pins 'CDN' and 'Q' on cell 'mp_dpwm1/DFF_reg[10]'0 a4 u; g9 w# ~1 ^# \& Q6 F8 ?
to break a timing loop. (OPT-314)
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! }: }! g A0 x% e6 B要怎麼判斷這些warning是必須要解決的
8 n! Z7 o& s* d- P& P }) K因為我還可以把波型合成出來
5 L8 [0 q/ c6 {: C可是我怕最後layout部份會有問題, v7 |, {- h5 [$ Z" a
5 W$ }; s8 ]0 Z[ 本帖最後由 小人發 於 2008-4-9 08:32 PM 編輯 ] |
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