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[問題求助] 靜電放電測試

[複製鏈接]
發表於 2008-4-12 00:55:01 | 顯示全部樓層 |閱讀模式
剛剛研究了靜電放電( HBM & MM) JEDEC標準,實在需要很長的時間去進行測試。假設該IC具有數以百計的pin,很可能將需要超過1個月完成整個測試。這裡是否有任何人負責做ESD測試?
發表於 2008-4-12 08:07:37 | 顯示全部樓層
竹科閎康科技有此業務
7 ~: I" V# q/ Z電話在網頁就查的到了.......................
發表於 2008-4-12 11:12:12 | 顯示全部樓層
很多實驗室好像都有,但都在台北.# c: [( U4 l" |  r/ I3 |2 o
儀特好像就有可以去查ㄧ下
發表於 2008-4-16 13:02:11 | 顯示全部樓層

很多家實驗室都有啊

目前新竹地區有"宜特"與"閎康"兩家比較大% [& o) I& t7 g0 R; s4 O
我的建議是去閎康,會比較適合。7 w8 o  N* [6 _9 v; M
因為我本身工作性質也是有接觸到ESD測試: ?) t) K' ^& [1 n
測試多Pin需要花費時間比較長久,可是你們HBM是使用JECDE
' B2 G9 y, P2 C, r- K) i" G# S在Zap的次數明顯比軍歸來的少了。4 ]8 h5 Q- P% }& }+ @
 樓主| 發表於 2008-4-22 00:07:49 | 顯示全部樓層
my company is pursuading to MIL-Std ...
6 I1 [. a1 Z1 t6 X- Qactually any company need MIL-Std? Our application is not for military purpose....
發表於 2008-5-21 12:14:35 | 顯示全部樓層
For ESD test (HBM)3 |3 M- ]0 k" u3 j% w
The following are the test combination:7 e, F# B) O7 u5 Q0 S3 t7 C- G
1. Power to Power0 R. D8 s1 n) F* R" |" A
2. Power to Ground
* ]7 |& q! E& t9 y3. IO to Power
) d9 T9 X; e8 |6 G0 _0 q4. Io to Ground, ^" b, V* s2 Q; W+ z6 o4 d- w; h
5. IO to IO
7 E; g3 U% t; `2 d0 {3 ?5 {9 z(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)/ }) Z, n8 b# ?7 F# ]: @. x
" U8 }& p8 }3 L. t
the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
. y% E6 h; m8 y& C' `) W% VFor example: You have IO1/IO2/IO3/P1/P2/G1# J; Y7 V. t: e, Z4 H5 B0 l& _( G; f
2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)1 z2 S* j& U9 h4 b" A
So for high pin count it will take a lot of time. But it won't take more than a week(for one chip). & n, O: |, `! }% Y! N% B
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For your reference.
發表於 2008-5-23 15:02:54 | 顯示全部樓層
樓上的Jason...據我所知大部分的IC設計都會跑去宜特做ESD...為什麼你要特別建議去閎康做呢??/ d4 p2 n! K" `& x; V7 M# A
有什特殊原因嗎??會比較適合的邏輯是什麼??是否可分享一下心得??感恩~
 樓主| 發表於 2008-5-26 21:15:09 | 顯示全部樓層
thanks wesleysungisme for your answer.! p" e0 S0 i* ]1 _$ y, W! b
as our pin count is over 1000 and no. of power is ~ 20, so it's quite time-consuming. 2 a  G  ]" Q- r( F# J
and there is technical issue about bonding all the dies into COB for ESD zapping, i wonder if anyone could share their practise? we feel difficult to strictly follow JEDEC standard.
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