靜電放電測試

wesleysungisme

For ESD test (HBM)
! i1 t7 T, s$ p: gThe following are the test combination:
( G8 p! ]8 p+ g6 a1. Power to Power
/ s+ s6 H* M3 |, n1 i  r" V2. Power to Ground
3. IO to Power
4 M- x5 k" |& p/ w; |. `4. Io to Ground
5. IO to IO
(different power domain need to be treated as different power. For ground usually you can treat as one group_silicon use substrate as common ground. But if you measure two different ground pin/ball > 2ohms. It should be seperated as 2 grond.)

3 P- c' g: b( r" ~the total zap time fomula will be~ 2(+/- polarity) X (IO#X(P#+G#)+IO#+P#X(P#-1)X(P#-2)X...X1+P#XG)
For example: You have IO1/IO2/IO3/P1/P2/G1
2x((3X(2+1)+3+2X1+2X1)=25(multiple the zap interval)
So for high pin count it will take a lot of time. But it won't take more than a week(for one chip).

For your reference.