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8 Failure Modes, Reliability Issues, and Case Studies 2286 r% B) g" k) b4 n, ?% H2 U
8.1 Introduction 228
' \( o3 p" e2 \: O) e9 T8.2 Failure Mode Analysis 229& g1 S& i; b m, n. h
8.3 Reliability and Performance Considerations 238& q: _* Z; X% w" v' _1 C2 L x
8.4 Advanced CMOS Input Protection 239
# m5 ~% K6 M) j Z6 a" e8.5 Optimizing the Input Protection Scheme 242
" ^7 M# k' \/ I. N( h4 ~8.6 Designs for Special Applications 249
/ H+ w3 v8 I& {; i+ r: H/ I8.7 Process Effects on Input Protection Design 253) Q1 u- G1 P$ s+ X# R# W: j
8.8 Total IC Chip Protection 255" U# q7 C9 P' O" M% e
8.9 Power Bus Protection 256# }$ O8 W( c( n' a% ^
8.10 Internal Chip ESD Damage 2583 R5 P+ m: c6 D5 s7 H
8.11 Stress Dependent ESD Behavior 263; M' [3 t3 H1 p ] r% c
8.12 Failure Mode Case Studies 267
; H a& u! v0 D* Y/ q" R8.13 Summary 271/ w1 B4 N' K4 }+ d4 \9 l
Bibliography 272, p) Z* C; } L4 J# _
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