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[問題求助] 關於ESD input and output pin 保護電路設計

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發表於 2010-5-10 14:38:41 | 顯示全部樓層
Per my experience ,Diodes + RC-Control , inverter and PowerClamp is better for out pad
1 u+ S$ v  V; u9 |" A5 T: P6 O. P+ RGenerally speaking ,the root cause of ESD failed is from below.& F# V! H6 o+ x$ o1 ]4 S) V
<i>clamp NMOS's ability., q: @1 ]/ q1 a1 q; I# c( P
<ii>clamp NMOS's turn-on rate.
% S0 Z* e* _; X. k" e<iii>Not follow design rule.......................
  n* b3 q& G) g1 K% Y! J: r6 UAs we know ,RC-control is to keep clamp NMOS off when IC is on normal operation.(us)
; H; J' e, u  Z6 _  QWhen sufferred ESD pulse(ns),GGNMOS be turned on by coupling .7 `+ A( `/ G- L+ p: a
If adding inverter between RC and clamp NMOS,it will speed up clamp NMOS turned on./ M! i/ R* A8 U/ ?& g$ u
Just for reference !!!
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