DFTC + ATPG Flow 中 scan_en & test_mode 問題

lee100

actually  scan enable signal can be shared with function pin, user have to insert control logic ("AND" gate for example, one of AND gate input connected to original function pin, another AND gate input connected to scan test mode signal and output of AND gate connected to scan enable pin of scan flip-flop). User should aware that fault coverage of cloud logic may dropped.