ESD Implantations of 0.18um CMOS

semico_ljj

ESD Implantations for On-Chip ESD Protection With Layout Consideration in 0.18-m Salicided
CMOS Technology
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' A" j7 K  t* ]4 A: T; v: C! vIEEE TRANSACTIONS ON SEMICONDUCTOR MANUFACTURING, VOL. 18, NO. 2, MAY 2005
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' Q& \( e* b" g) ~2 ]$ ]Abstract—One method to enhance electrostatic discharge (ESD)robustness of the on-chip ESD protection devices is through process design by adding an extra “ESD implantation” mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18- m salicided CMOS process is investigated by experimental testchips.
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