十項全能 vs. 三項鐵人？Layout達人如你未來最需要加強哪三項吶？

ranica

招聘公司：A famous analog IC company
招聘岗位：Mask Designer / Physical Layout Designer
! R% n/ k- c2 c- ]; V+ M+ v9 k5 s工作地点：Hangzhou
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. Y1 h. t2 s* M. u, X& ?岗位描述：
Position Overview XX Technology Corporation is seeking an enthusiastic Mask Designer / Physical Layout Engineer in our Hangzhou, China Design Center. We develop a wide range of high-performance power, analog, and mixed-signal ICs using our unique Bipolar, Bi-CMOS, and CMOS processes. We compete in a wide range of markets including:
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• DC/DC Converters • High Resolution Data Conversion • Interface Products • Portable Power Management • Hot Swap Controllers • High Performance Amplifiers and References • Automotive Electronics

) f& z# v7 d/ M- q$ B1 M6 i/ ?Responsibilities include (but are not limited to):
• Layout schedule estimation.
3 }1 H9 U; y' v5 q6 F% {' s• IC layout floor planning.
• Layout of analog and digital circuits.
# z) x' R) v" p6 y1 J  z' |+ b% @8 Q• Cell level verification and parasitic extraction.
• Chip/Top level routing and interconnect.
• LVS and DRC checks using Cadence Dracula and Assura.
' m% }- w& H1 R! t. B! p• Tape out/Stream out/PG.

ranica

职位要求：
+ @( \6 ?+ B' X/ w! U9 M" kRequired Skills The ideal candidate must have the following key requirements for this position:

• Bachelor or master’s degree in Electrical Engineering or related major.
• Five years of relevant IC layout experience.
/ j+ R* w# F* H1 U9 e; R8 _• Strong background in analog layout.
• Familiarity with Cadence tools (Virtuoso, Layout XL, Assura, Dracula).
• Layout experience with bipolar, CMOS, and BiCMOS technologies.
3 W1 `% ^! S' ^• Working knowledge of Linux operating systems.
. p  H4 e( b$ B7 R  P• Experience with full chip layout including PG to the mask shop.
• Knowledge of semiconductor device and fabrication principles is a plus.
• Ability to work independently.
• Great attention to detail, communication skills, well organized

ranica

招聘公司：A famous European IC company
. d) L: S/ W" _% |, w! u招聘岗位：Layout design engineer
4 G2 w) v: _" _- `+ |) G9 _  _工作地点：Shanghai
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1 {/ r: F$ H- S% k# z$ G' t岗位描述：
Roles and Responsibilities Full-custom layout of analog and mixed-signal circuits Estimation of efforts and schedules for layout projects Floorplan generation for analog layouts Optimization of analog layouts for low parasitics and low area Close cooperation and interaction with international teams
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职位要求：
Qualification Requirement (e.g. Education, Working Experience, Knowledge, Skills, Language, Competence, etc) Bachelor or master degree in Electronics, Communications, Computer Engineering or equivalent, 3+ years Experience in analog full-custom layout (CMOS) Experience in running DRC, LVS, and PEX preferably with Cadence Virtuoso Understanding of CMOS process flow Self motivated, excellent communication skills and team spirit English written and verbal Willingness to work and interact in international teams