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On-Chip ESD Protection for Integrated Circuits8 r0 }# u D4 _6 W( q, R' y
An IC Design Perspective
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Albert Z.H. Wang5 _% w$ k+ S* r% t/ t( k3 t
Illinois Institute of Technology, Chicago, USA. K& l: m+ E9 n; }9 X7 ?1 a
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Dedication. & X! ], _/ x2 p; p+ i4 b
Acknowledgements.
+ V' K7 M" v: X& q- fPreface. 5 E! t% M# ?4 n& Y0 r3 D
1. Introduction. 2. ESD Test Models. 3. ESD Pr
* Z; z% C+ F% O/ i+ U- xDevice Solutions. 4. ESD Protection Circuit Solutions. 5. Advanced ESD Protection; Mixe
0 z# f1 t8 {6 Y" Kand Whole-Chip ESD Protection. 6. ESD Failure Analysis and Modeling. 7. Layout and Te5 i+ y1 u, j2 i
Influences on ESD Protection Circuit Design. 8. ESD Simulation-Design Methodologies. 92 l. ~6 a+ x* m2 q+ _9 P: Q
Circuit Interactions. 10. Conclusion Remarks and Future Work. . K ^) U6 N3 ^! U; u& {+ H
Appendix A: Summary fo; J# @; s( J1 i" ]% s% {' q
Standards. References.
; s0 f2 w Z B; s* H9 NAppendix B: Commercial ESD Testing Systems. & E5 [0 e- m1 n2 G
Appendix C: E
2 v+ v* h8 a" Z& iProtection Circuit Design Checklist. Index. |
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