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Senior/Staff DFT Design Engineer. A% s/ c" ~7 C! W0 W$ ^1 K$ `
公 司:A famous IC company
; G6 f+ Y$ T8 S+ Q& Z" z/ ?工作地点:上海
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1 Y6 W. ~( E* i) {* ?Description:
7 `; J: s! u- s5 l- z" u- Block, IP and SoC level DFT implementation (bscan, scan, mbist, jtab, analog test structure, etc.) 4 q2 V* l1 s- w5 E
- work with IP vendor (internal/external) to analyze DFT integation issues
6 k# h& @9 q2 e$ z- DFT STA, constraint generation, formal and timing closure 4 A! v/ f4 l6 j, f1 g8 l: ~
- DFT flow development and maintenance ) p u# z0 W! h1 i R) |6 @
- test vectors generation and verification
. H4 V, C2 t) G# X$ h+ r: W- interface to backend team on physical design and timing closure ; Y( s6 j6 e) n9 Z9 f
- interface to test engineers on ATE and vectors bring-up and debug
( z2 A4 m1 P8 |- x1 O- chip DFT quality sign-off
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, Y1 z A" l# |4 f- \9 l, H3 oQualifications:
, g- i; ?4 K! A/ c- m2 L0 O- x3 xMust have:
/ \! h+ U# k- X3 h- minimum 4+/8+ years of DFT design and integration experience
, | T: o. S% s1 \5 [- hands on DFT implementation experience (bscan, mbist, scan, IP testablity integration, at-speed 2 a: o- q, f9 G$ _
scan, IDDQ test, ATPG and fault simulation)
8 [3 D% x" B4 k- expertise with DFT tools from Synopsy, Mentor, Syntest and Logic Vision
! A/ q8 t# t, \ q$ Q/ j- strong logic design and verification backgroud solid experience in STA
7 J' s, V7 y, T4 D- proficient in Perl, tcl and shell programming
; x- p1 ^. H' Q3 _& B- BSEE degree or above 7 m, ?+ x+ ]7 O, n$ d
- good team work spirit 6 {( J+ P c. _* k, J
" C9 s; @& u' O2 ]4 A! p, R7 hNice to have:
7 W3 x. n2 M/ [& X$ G- familiar with DTV/STB architecture, design, and IP : ~- p, S7 t% S9 U3 [ B
- proficient in C++ and system verilog |
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