SVTC Technologies Selects Synopsys' Manufacturing Tools to Accelerate Time to Commercialization | 7/14/2010 |
Open-Silicon Integrates 50 DesignWare Interface and Analog IP Products with 100% Silicon Success | 7/7/2010 |
ARM, IBM, Samsung, GlobalFoundries and Synopsys Announce Delivery of 32-/ 28-nm HKMG Vertically Optimized Design Platform | 6/17/2010 3 L* M$ S/ P* C$ ^, A6 P
|
PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances | 6/17/2010 |
Synopsys Delivers Optimized Lynx Design System for Common Platform 32/28-nm Technology | 6/17/2010
( Q' n. c* G$ Q: { |
Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories | 6/17/2010 |
Synopsys Unveils StarRC Custom 3D Extraction Delivering 20X Speedup | 6/17/2010 |
Synopsys Delivers Comprehensive Custom Design Solution for TSMC Analog/ Mixed-Signal Reference Flow 1.09 }% S9 v+ B- m8 i7 Q5 N7 e
| 6/11/2010 . f0 `0 |1 T2 N1 l
|
Synopsys to Acquire Virage Logic ! Y- P4 {5 e- B6 r7 \
| 6/11/2010 + B b8 Z% ~0 Q) a9 Z* {
|
Synopsys and IEEE-ISTO Launch Technical Advisory Board to Evolve Interconnect Modeling Standard
0 O+ \4 f( _( @ | 6/7/2010 9 P# y% p) K% _( }% h8 j/ N
|
Synopsys Announces Synphony HLS Support for Xilinx Virtex-6 FPGAs
/ I* b% W) e* `: l, P4 ~ | 6/4/2010
4 y$ y- { \7 u4 Q9 A4 S3 W |
Synopsys Press Publishes "The Ten Commandments for Effective Standards" + _/ q- Y. z9 N+ h, V
| 6/4/2010
6 D% L8 O! V8 l9 P& | |
Synopsys Collaborates with SMIC to Deliver USB Logo-Certified DesignWare USB 2.0 nanoPHY in SMIC's 65-nm LL Process Technology ! C5 y. r( X" ?9 ?; g7 j
| 5/13/2010
& Q& s* A- W2 I. @6 m# @ |
Latest Synopsys IC Compiler Release Delivers More than 2X Speed-Up, Enhanced In-Design Technology and Production Support for 28/32nm
) h' K- _% ?# v, i2 T5 l2 J | 5/7/2010
; f4 ~& u% [0 w7 _$ A: G; b# } |
Synopsys Unveils Ethernet Controller IP with New Audio Video Bridging Feature
( q8 e+ w2 j3 s2 L. q: Z | 5/7/2010
5 Z3 N( _ w4 ?. `" R9 h, x3 A& i |
Synopsys Launches Industrys First MIPI DigRF v4 IP
* K( j. c" M- N* \. Y ~; V | 5/3/2010
4 g0 J; d' Q, S! } |
New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces
: T; V k8 }3 H9 c | 4/28/2010 4 @ k( _) F7 V. N( S
|
Synopsys Announces Support for Actel's New SmartFusion Intelligent Mixed-Signal FPGAs
' `" Y) M& k! O _3 I5 H | 4/22/2010
6 c6 Y- l1 q. m* k" x7 n+ P |
Synopsys Introduces the HAPS-60 Series of Rapid Prototyping Systems " C& Q* U$ q7 X; [ |
| 4/19/2010
1 S: G! I! J" k; D" U( ]4 }; ^ |
Synopsys Expands IP OEM Partner Program with Two New Members
+ a3 q4 [1 E6 D: X: E- V | 4/14/2010
1 O7 Q! n( s3 `7 W( m. m |
Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards In a Single PHY
; {& Y" \% E, K' h D | 4/7/2010 ! f5 Y. Z, Y" o `
|
Synopsys' DesignWare SuperSpeed USB 3.0 IP Receives USB-IF Certification
# u$ }1 i! V% W- W | 4/5/2010
2 ]- ~- f7 H1 M! ^. c4 o6 r' u |
SiliconBlue Selects Synopsys as FPGA Synthesis Partner for Its iCE65 mobileFPGA Family 3 I/ X0 L7 H' ?1 Y
| 4/1/2010 ) |0 U( @, K, {: t1 O+ M
|
Synopsys Galaxy Implementation Platform Enables First-pass Silicon Success on Infineon's 40-nm X-GOLD 626 Wireless Product
( v/ W4 t g6 _' c | 3/30/2010 b# x4 R. ?5 P
|
Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route
: ~" `. u6 b$ J4 T7 C9 k/ { | 3/29/2010 ! M- ~# m/ R9 O
|
Nationz Technologies Achieves First-Pass Silicon Success with CustomSim Mixed-Signal and VCS Functional Verification Solutions 0 n) s3 i/ l# z1 M* r) ]% o8 C
| 3/23/2010
3 q r% s& y& d8 I& U* C' H |
Renesas Technology Adopts Synopsys Proteus OPC for 28-nm Development
7 k+ I4 z" {# J5 q4 \4 k | 3/23/2010 : F; v7 h: A N0 j1 t& r" q$ t' n+ J
|
Synopsys Completes Acquisition of CoWare
% @4 z1 _# U6 K% W& x% n7 ? | 3/23/2010 ' M5 k& y! S8 W" H1 G, p8 N G
|
IMEC and Synopsys Collaborate on 3D Stacked IC Development
1 }# b# I T! n+ H; H8 N* l | 3/10/2010 6 Z" z/ d* s2 _6 J* [0 b- ]
|
Synopsys Galaxy Custom Designer Accelerates Analog/ Mixed-Signal Engineering Productivity with Built-in DRC Visualization and Correction
" M9 W9 e% [, u4 v- u4 _' @7 U | 3/10/2010
/ f3 Y) T( v0 C0 ]! n1 e3 ?; ?# l- n |
Yamaha Tapes Out Graphics Chip with Synopsys Design Compiler Graphical
: J& k' ^: ?. R4 t4 c | 2/9/2010
8 d0 i9 A0 G+ L% p3 H8 g |
APAC IC Adopts Synopsys Galaxy Custom Designer Solution for Analog/ Mixed-Signal IC Design Services
, ?' J0 t Y: M0 G3 t | 2/8/2010 5 @, [0 K8 o* j, o; a, n$ L2 a9 {
|
Synopsys to Acquire CoWare + H' A6 ?& b* L6 Q$ F# a
| 2/8/2010 6 |4 @' j! T8 N" ^5 q; F+ g( u
|
Synopsys Acquires VaST Systems Technology % F6 g" T( |; ^9 ?
| 2/3/2010 1 Y' m4 I- U6 V R4 ?9 @
|
Synopsys Expands DesignWare IP Portfolio with MIPI IP Solutions
# x/ X' S6 Z. O ]/ Y/ A8 S. @- A | 1/25/2010 - Y+ n4 N7 C1 ^: w6 Q7 y
|
Synopsys Launches DesignWare HDMI 1.4 Tx/Rx Controller and PHY IP Solutions for 40-nm Process Technologies
$ C2 r0 W. g/ j6 m' J9 v* Q | 1/25/2010
/ N/ }/ ^: l+ w2 D" c. A7 d& U |
Toshiba Information Systems Standardizes on VMM-LP Low-Power Verification Methodology
+ M' s' T' |5 E- f* B | 1/25/2010 ; w- a1 Q% ]! v% M
|
Synopsys Announces DesignWare Protocol Analyzer for Verification of SuperSpeed USB 3.0-based Designs
m4 ?2 i, f! J | 1/13/2010 0 t( v) e& K8 v. d( H2 w
|
Synopsys Introduces SystemC TLM-2.0 SuperSpeed USB 3.0 Models : `* g) ?" b9 P" x
| 1/12/2010
% r2 h' I7 m$ K' m |
Synopsys Multicore Technology Speeds Timing Sign-Off by 2X ) t |; f8 K8 [1 d) }5 P0 c- y
| 1/11/2010
0 t2 o b; U3 t* r4 ^$ g4 [ |