SVTC Technologies Selects Synopsys' Manufacturing Tools to Accelerate Time to Commercialization | 7/14/2010 |
Open-Silicon Integrates 50 DesignWare Interface and Analog IP Products with 100% Silicon Success | 7/7/2010 |
ARM, IBM, Samsung, GlobalFoundries and Synopsys Announce Delivery of 32-/ 28-nm HKMG Vertically Optimized Design Platform | 6/17/2010
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PrimeTime 2010 Scales Timing Analysis Beyond 500 Million Instances | 6/17/2010 |
Synopsys Delivers Optimized Lynx Design System for Common Platform 32/28-nm Technology | 6/17/2010
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Synopsys Unveils Galaxy Characterization Solution for Standard Cells, Complex Macros and Memories | 6/17/2010 |
Synopsys Unveils StarRC Custom 3D Extraction Delivering 20X Speedup | 6/17/2010 |
Synopsys Delivers Comprehensive Custom Design Solution for TSMC Analog/ Mixed-Signal Reference Flow 1.0: E' \# Q# j/ D
| 6/11/2010
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Synopsys to Acquire Virage Logic ' `5 R6 A0 O3 V: {: C$ Q+ D" j6 L
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Synopsys and IEEE-ISTO Launch Technical Advisory Board to Evolve Interconnect Modeling Standard 3 |, H$ b0 t1 V
| 6/7/2010
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Synopsys Announces Synphony HLS Support for Xilinx Virtex-6 FPGAs
# L8 h$ }; x/ r! S* V, G5 l) n | 6/4/2010 ' S h" F# b1 c* _4 s( ^
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Synopsys Press Publishes "The Ten Commandments for Effective Standards"
2 |$ ?( K/ H1 G# `& v | 6/4/2010
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Synopsys Collaborates with SMIC to Deliver USB Logo-Certified DesignWare USB 2.0 nanoPHY in SMIC's 65-nm LL Process Technology 9 h$ y3 @* O* y' b r: v
| 5/13/2010
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Latest Synopsys IC Compiler Release Delivers More than 2X Speed-Up, Enhanced In-Design Technology and Production Support for 28/32nm
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Synopsys Unveils Ethernet Controller IP with New Audio Video Bridging Feature
3 k" P) l& ]* o7 ?8 E | 5/7/2010
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Synopsys Launches Industrys First MIPI DigRF v4 IP & p& N7 R& n3 H! B, u6 B
| 5/3/2010
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New Synopsys Universal DDR Controllers Improve Performance and Reduce Cost of Embedded DRAM Interfaces
; c' |4 P; b0 e2 C, u | 4/28/2010 3 f3 i7 @* F1 F* u" v+ x; p
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Synopsys Announces Support for Actel's New SmartFusion Intelligent Mixed-Signal FPGAs
1 c2 T) O$ g$ U$ ~: C0 r$ } | 4/22/2010 2 x8 v! b0 A) y/ b9 Y+ n" K
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Synopsys Introduces the HAPS-60 Series of Rapid Prototyping Systems
; y7 g* V9 t7 D' F( J; W | 4/19/2010
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Synopsys Expands IP OEM Partner Program with Two New Members
& B: b$ o' L f- O6 q | 4/14/2010 * _0 h5 {- i3 b" [, |* E
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Synopsys DesignWare DDR multiPHY IP Supports Six DDR Standards In a Single PHY
; S, \: _; G6 i! Y# M& O | 4/7/2010
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Synopsys' DesignWare SuperSpeed USB 3.0 IP Receives USB-IF Certification
* {( X( @% S. c6 L8 n% V | 4/5/2010
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SiliconBlue Selects Synopsys as FPGA Synthesis Partner for Its iCE65 mobileFPGA Family ; p( M% d, W: u6 W
| 4/1/2010 $ r: O+ E8 u- P5 Q9 R0 X
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Synopsys Galaxy Implementation Platform Enables First-pass Silicon Success on Infineon's 40-nm X-GOLD 626 Wireless Product - A2 W5 ^; `* A; V7 n, ]' a7 A, c s
| 3/30/2010
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Design Compiler 2010 Doubles Productivity of Synthesis and Place-and-Route
# R/ o& H+ S3 d' J | 3/29/2010
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Nationz Technologies Achieves First-Pass Silicon Success with CustomSim Mixed-Signal and VCS Functional Verification Solutions
& y- s* N; I+ P# x: S* _. v* ~6 {/ p Z1 y | 3/23/2010
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Renesas Technology Adopts Synopsys Proteus OPC for 28-nm Development $ I i# @ U+ v# l- \* v4 W
| 3/23/2010
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Synopsys Completes Acquisition of CoWare
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IMEC and Synopsys Collaborate on 3D Stacked IC Development J/ ?4 A7 Y1 N6 H0 r
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Synopsys Galaxy Custom Designer Accelerates Analog/ Mixed-Signal Engineering Productivity with Built-in DRC Visualization and Correction / b: m6 a: E2 m! D, {
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Yamaha Tapes Out Graphics Chip with Synopsys Design Compiler Graphical b8 S" \1 t) y, o6 r4 s, D. C
| 2/9/2010 6 S: q9 g: k7 {1 K: ^
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APAC IC Adopts Synopsys Galaxy Custom Designer Solution for Analog/ Mixed-Signal IC Design Services
6 M, b/ `1 Q% J+ Z | 2/8/2010
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Synopsys to Acquire CoWare 4 |* |) R |2 |( S
| 2/8/2010
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Synopsys Acquires VaST Systems Technology . x W) Z8 w( z8 d0 ^. t6 `
| 2/3/2010 0 F9 {2 ~; Z9 C: j: k. \; l' A
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Synopsys Expands DesignWare IP Portfolio with MIPI IP Solutions
8 y% O/ I9 {2 \) Q: C; M9 T | 1/25/2010
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Synopsys Launches DesignWare HDMI 1.4 Tx/Rx Controller and PHY IP Solutions for 40-nm Process Technologies ; z* }* u3 @. O+ }& I
| 1/25/2010
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Toshiba Information Systems Standardizes on VMM-LP Low-Power Verification Methodology 5 U# ]* N2 F; f
| 1/25/2010 % n3 b6 E. W/ t" L9 ^( a; L
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Synopsys Announces DesignWare Protocol Analyzer for Verification of SuperSpeed USB 3.0-based Designs
$ K' A' G# T8 R/ H: |4 }8 m, t l) N | 1/13/2010 ; M/ l& V( W) K# u& W: Y! s! E$ r
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Synopsys Introduces SystemC TLM-2.0 SuperSpeed USB 3.0 Models
/ ^+ {2 z0 A @; M+ f0 \! C \+ U | 1/12/2010
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Synopsys Multicore Technology Speeds Timing Sign-Off by 2X
( P5 f$ a. {, U, ^8 m+ t3 M. u | 1/11/2010 , X+ s6 ?$ d0 N1 V/ f
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