|
Junior Physical Design Engineer
8 s% p" } D( y5 t1 ?0 _
" ~7 ?, q, g9 Q9 j公 司: famous IC company
# S0 c# p$ _: V* s( {) f O3 c& {工作地点:北京, J/ Y0 b3 ]& W* p# m1 u/ f
2 z6 ~0 v6 m% h" N; E- BPosition Tasks, Duties and Responsibilities
! q& z; u ?+ h: {/ w, CThe ASIC Physical Design Engineer will:
% \* r$ n" i, ^* A0 |9 h Complete third party IP integration and ensure vendor guidelines are followed. % V, w" Z2 d7 S
Responsible for physical verification (DRC/LVS).
3 Y: C9 O/ ]3 t: q9 {) I IO ring design, fullchip floorplan.
* k3 ~/ O. N' n4 d9 F Block level implementation.
& D# ]6 s T2 s7 @! V Work with front-end engineers to resolve problems and achieve design closure. 9 |; E5 `* e, m- }5 s# _
& T2 _* B9 }$ X. C6 R( m- W
Candidate Qualifications: ! S/ M _! ]: w3 [8 V
Candidate must: 2 t$ z8 F/ e3 @$ S( d/ `+ E' L# ~
Hold BSEE (MS preferred).
6 F* i! N' G+ N4 H6 K1 G$ h Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
* ^8 r/ e* k+ ^% P0 [ Be able to complete block and chip level tapeout quality LVS and LVS and DRC. 9 R) Y, F7 v3 f
Have the ability to independently identify and resolve design, tool, and flow problems.
) U+ A" M+ p5 W7 k" Q- j Have related timing and physical concept.
8 b3 J, A# p& S ^9 j1 W Be able to design and implement physical design strategies and methodologies for deep submicron designs.
% d6 D: X6 x1 X3 t5 g Familiar with EDA tools. 2 M5 F0 r8 U( P; `; F. p, D
Familiar with Linux environments. . [4 q- s& {' R6 P5 g4 }
u7 X9 B" {$ D+ W
Any of the following is beneficial: & L2 }9 n: K& H0 H" {* d+ B, \4 V; v
STA constraint design
! t$ Y( c9 ?6 i% p3 s! u Equivalence checking ?RTL to gates, and gates to gates. |
|