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Junior Physical Design Engineer
- R8 N9 \! h; o* P" o: V' |- N" h8 U$ V公 司:A famous IC company/ ]6 o, d8 P; F$ h' @3 ]7 J# v) X
工作地点:北京+ x) J) A, g! P1 v U7 K
7 Q/ L2 T5 ^, M7 V6 @# IPosition Tasks, Duties and Responsibilities 6 c- M8 K3 |# a. P* j! W: D6 L7 {
The ASIC Physical Design Engineer will: ) h7 j2 ]" o8 B; |3 w& u
Complete third party IP integration and ensure vendor guidelines are followed.
0 ^2 T7 r- H9 b* w Responsible for physical verification (DRC/LVS).
; A( p! r9 S( T7 Z0 ]7 Y+ ~ IO ring design, fullchip floorplan.
0 ~. S2 N5 C3 f/ G* C* O( X Block level implementation.
9 X. z8 ]3 G; L$ Y Work with front-end engineers to resolve problems and achieve design closure. " d, O1 [' d) ] R
% d3 Z, C' E' _: d! S, K1 tCandidate Qualifications: ) F1 l& m" s5 Q" y3 B8 C
Candidate must:
) j, N" f0 b# z9 ], c Hold BSEE (MS preferred). . X- T M2 V: i
Have minimum of 3 years hands-on experience in full flow IC back-end physical design and verification
* h. `# T* z4 E! X Be able to complete block and chip level tapeout quality LVS and LVS and DRC.
7 G. P$ }* v0 j- S- r6 W& V; e) D Have the ability to independently identify and resolve design, tool, and flow problems. ; e* P% B& n. g% }) L7 Z- Y% H
Have related timing and physical concept.
/ k' O+ i7 M$ X6 G- r, b( x2 |5 y Be able to design and implement physical design strategies and methodologies for deep submicron designs.( Z: B0 }' n& P7 Y) ~' U* o4 t9 `# f
Familiar with EDA tools.
; t4 S& Y0 z! C; t( k8 m# K4 c! x Familiar with Linux environments. ; f) s; G2 A) d, u
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Any of the following is beneficial: ' ?# ?3 I; {: F0 j
STA constraint design % z$ k! C8 [0 U
Equivalence checking ?RTL to gates, and gates to gates. |
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