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0. Check circuit topology and connectivity.
- a/ G& P1 C0 K* i5 B5 s2 fThis item is the same as item 0 in the DC analysis.
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7 z4 S$ T% |% z8 K4 V- P0 i. P3 G3 e1. Set RELTOL=.01 in the .OPTIONS statement.
3 r. q, K* x$ ] LExample: .OPTIONS RELTOL=.01) @& a6 q7 v' U8 u3 Q: ^& Z" }
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2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.
b5 P: u6 @7 V/ S5 J, w0 EExample: . OPTION ABSTOL=1N VNTOL=1M6 c" Z: z2 p. G& N
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3. Set ITL4=500 in the .OPTIONS statement.: q5 R) {. @1 s' C8 j
Example: .OPTIONS ITL4=500
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, C: O$ {6 Y, N+ Q- a: p5 {. x% [4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.# P/ n+ m! p, y. O
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5. Reduce the rise/fall times of the PULSE sources.: E1 E) m+ V) Q9 O5 e9 h
Example: VCC 1 0 PULSE 0 1 0 0 0
O' {0 x* L0 a; P' {becomes VCC 1 0 PULSE 0 1 0 1U 1U
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5 P; j% V5 x- ~ {6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources. q) |9 I( D' |9 E3 S' i
Example: .OPTIONS RAMPTIME=10NS& e+ ^1 O. L5 I/ C* n3 X1 ?! \
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7. Add UIC (Use Initial Conditions) to the .TRAN line.
* l* g5 o% h R3 |Example: .TRAN .1N 100N UIC
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% Q& D- c) o4 z W$ c# ~8 h( I; `8. Change the integration method to Gear (See also Special Cases below).
+ F' q; \6 h* }* t1 L# mExample: .OPTIONS METHOD=GEAR |
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