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0. Check circuit topology and connectivity.
5 A+ L& p, r1 N2 U' Y; GThis item is the same as item 0 in the DC analysis.
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% s! k* y" O9 p% F1 A# s2 `+ w8 O1. Set RELTOL=.01 in the .OPTIONS statement.
1 N- M& |1 f4 I0 }Example: .OPTIONS RELTOL=.01
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8 m) L; U! v; B1 c2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.+ \* h' W8 u# K- X" z
Example: . OPTION ABSTOL=1N VNTOL=1M
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9 L$ H- z' @! I" f3. Set ITL4=500 in the .OPTIONS statement.2 C: i4 t' |, h# y( e0 D3 V% T0 S
Example: .OPTIONS ITL4=500
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% t% [' w3 V+ m/ G- A; V' w4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.
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1 X; @, H& p+ R* S \5. Reduce the rise/fall times of the PULSE sources.
! u5 W* d7 z% p( F+ {/ ?, m# v5 ~Example: VCC 1 0 PULSE 0 1 0 0 0
4 d" \6 s9 y: `) R! o$ c& z9 qbecomes VCC 1 0 PULSE 0 1 0 1U 1U$ ~2 a$ g2 ]0 k1 P( A B
$ F1 I/ C! k, r: A. U) @6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.+ _0 o8 k7 s D' j
Example: .OPTIONS RAMPTIME=10NS
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7. Add UIC (Use Initial Conditions) to the .TRAN line.5 v% V. _4 i2 P- p3 c) {& b: ^8 g
Example: .TRAN .1N 100N UIC
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8. Change the integration method to Gear (See also Special Cases below).
3 y$ W: K% [8 [& D+ v& D8 PExample: .OPTIONS METHOD=GEAR |
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