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0. Check circuit topology and connectivity.( ~/ ~& H0 W! |
This item is the same as item 0 in the DC analysis.
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1. Set RELTOL=.01 in the .OPTIONS statement.
, K" u) J1 q: v" O5 ^# mExample: .OPTIONS RELTOL=.015 U+ C' ?% l e: v7 R ?
6 E t( S, A7 Y5 X" ?2. Reduce the accuracy of ABSTOL/VNTOL if current/voltage levels allow it.& Y' {5 S j$ ^: U" l. u: r% i
Example: . OPTION ABSTOL=1N VNTOL=1M- ]6 A; t4 ~+ G6 `, o
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3. Set ITL4=500 in the .OPTIONS statement.: a1 t) q2 V2 n4 V) |4 @
Example: .OPTIONS ITL4=500% n' n: _7 U. _4 [/ p6 h" ?
& G0 P+ m3 I! t/ A4. Realistically Model Your Circuit; add parasitics, especially stray/junction capacitance.
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1 }: T! m3 n4 K; p/ k: ^5. Reduce the rise/fall times of the PULSE sources.9 x" ~' K/ t& H' Z8 l; y$ G
Example: VCC 1 0 PULSE 0 1 0 0 0
) Z4 w& |# k3 R2 hbecomes VCC 1 0 PULSE 0 1 0 1U 1U
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( r$ F4 J+ m* d4 U X/ n8 p6. Use the .OPTIONS RAMPTIME=xxx statement to ramp up all of the sources.
+ }+ b7 I6 R5 F# FExample: .OPTIONS RAMPTIME=10NS- C+ C: V( f8 d$ }9 {6 o# S
2 O" Y( b1 c& J4 t( X7. Add UIC (Use Initial Conditions) to the .TRAN line.
% X, v2 C' C5 j, p+ KExample: .TRAN .1N 100N UIC
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8. Change the integration method to Gear (See also Special Cases below).8 C6 k5 N9 ~- d; D! o
Example: .OPTIONS METHOD=GEAR |
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