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AMD Geode LX 800@0.9W處理器
General Features
c$ N9 a9 T9 {" w8 c- R2 J5 C■ Functional blocks include:
/ d+ F6 p, M# `— CPU Core
) |/ m1 ]* F7 b! b— GeodeLink™ Control Processor
; ]6 c: o4 I. m— GeodeLink Interface Units5 x+ U% g/ Z3 ]
— GeodeLink Memory Controller4 t2 c$ x) A9 }, k2 |
— Graphics Processor K! _$ @) G: |& G/ Q
— Display Controller2 I f1 P* j9 p
— Video Processor8 W* R, c( l7 [1 Z7 Y, _
– TFT Controller/Video Output Port" ?/ G! |3 ]6 i
— Video Input Port, {; J+ w: F2 E1 \( D$ O
— GeodeLink PCI Bridge
* T7 b6 D) {0 l; f1 r) y" T— Security Block, R+ s _: ]9 i9 h
■ 0.13 micron process
& C$ l+ V. @7 k0 L o■ Packaging:
( E$ B! c: D3 J1 T1 P: [— 481-Terminal BGU (Ball Grid Array Cavity Up) with
0 C1 S& J4 A& F$ o& i6 Binternal heatspreader" c' H! ^( l e! e* ^
■ Single packaging option supports all features- c0 ~, o+ q7 Y: n- E+ q2 ^
CPU Processor Features
' h7 U2 V- h) H, x# \. s■ x86/x87-compatible CPU core4 ~1 r7 x1 S: h
■ Performance:
+ L1 p1 m1 m, f" I+ Q& L— Processor frequency: up to 500 MHz) M2 M- v+ }( p! T c$ W+ ~2 e
— Dhrystone 2.1 MIPs: 150 to 450 a6 j# o. K. R+ Y, ^- p6 s
— Fully pipelined FPU
( Q, Y+ C" x; o1 I■ Split I/D cache/TLB (Translation Look-aside Buffer):0 g9 t ~ {" D8 p: |
— 64 KB I-cache/64 KB D-cache
8 C: X3 h' Z6 v4 }& E) B— 128 KB L2 cache configurable as I-cache, D-cache,2 G3 K+ f* }! T5 \& Q
or both
! V+ \1 e3 b' K6 d5 U/ `; @+ e■ Efficient prefetch and branch prediction1 M/ s; d8 _/ r$ k5 {8 x* c5 d
■ Integrated FPU that supports the MMX® and" `1 _$ P' W2 T; V/ C8 D ~
AMD 3DNow!™ instruction sets
3 X3 R3 B% W1 o( X) E C9 D/ V2 r% T■ Fully pipelined single precision FPU hardware with
. z0 b1 d* [% [: |2 |- z$ Zmicrocode support for higher precisions+ g0 e4 G' N2 ]: x8 L% @
GeodeLink™ Control Processor$ o4 _5 @% Z& q9 _6 U
■ JTAG interface:
; W, n) A/ E/ y$ w- V, @6 q— ATPG, Full Scan, BIST on all arrays
! \( w- O: Q- O, i3 P% D— 1149.1 Boundary Scan compliant
! g. O, `- W* U, f! J■ ICE (in-circuit emulator) interface$ M; e) p, Z* S( k
■ Reset and clock control
3 W" b O: j" J! D■ Designed for improved software debug methods and
1 h- h/ X4 \# ]" W5 [performance analysis0 C7 ?9 o z' J4 Z6 f: S z, O
■ Power Management:
1 q. a9 N- U# ~2 V— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
/ T6 }. }7 L, n$ F* k: Z+ W C9 h" t2 |500 MHz max power
0 J2 v9 N7 R2 k9 }— GeodeLink active hardware power management) c) Q$ Q% d& ]& i; K
— Hardware support for standard ACPI software power/ T" A( r4 J9 @9 |6 H5 V" A
management1 a. i3 e" a9 A9 |, S4 c
— I/O companion SUSP/SUSPA power controls
; P& ^/ s4 ]4 [$ k+ D: V— Lower power I/O7 Y6 n4 L) c5 O# Q
— Wakeup on SMI/INTR) H4 w. s: Z4 u
■ Designed to work in conjunction with the
$ R8 t7 Y' |- z X* a" \2 [) `AMD Geode™ CS5536 companion device& L1 r8 n, j( m l1 g! y
GeodeLink™ Architecture
/ r) l& [, E4 V, m A# s3 \■ High bandwidth packetized uni-directional bus for# z) o. g, Y4 m7 T: n$ I# l1 O9 H
internal peripherals; e9 p: i/ F. u6 Q' W
■ Standardized protocol to allow variants of products to be, ?2 ]. t& S2 L! M G
developed by adding or removing modules' b7 l& _8 j5 _$ c
■ GeodeLink Control Processor (GLCP) for diagnostics
6 r( T" P* M6 T, aand scan control& D4 K. k$ k" ]3 F/ B2 x
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
3 q7 ~ O4 M3 }) ]GeodeLink™ Memory Controller- a5 J6 F) j9 `' q0 `$ Z Z+ a
■ Integrated memory controller for low latency to CPU and0 d# k. g$ S" D: W+ G% _4 N
on-chip peripherals
3 F( V |/ h! g) k7 P( Y■ 64-bit wide DDR SDRAM bus operating frequency:2 a1 }! }. F, S
— 200 MHz, 400 MT/S5 b9 v3 S' k. Z# ?& G$ h# U
■ Supports unbuffered DDR DIMMS using up to 1 GB
* b0 M9 w% G4 g$ kDRAM technology( K" z9 T j) T, _# A
■ Supports up to 2 DIMMS (16 devices max)
/ H$ |* K Z% C+ |5 ?8 M2D Graphics Processor- u+ m' s. E; X# V/ s9 [) g3 O
■ High performance 2D graphics controller
& Z7 S' W8 H$ g1 `5 {1 k: Y1 j■ Alpha BLT0 s# U9 {4 m6 E5 l
■ Microsoft® Windows® GDI GUI acceleration:
: A3 f6 R; O. n/ m) E; Z+ y— Hardware support for all Microsoft RDP codes6 Z0 g0 ^3 a1 ^# I% p) _0 j
■ Command buffer interface for asynchronous BLTs% V. Z8 h3 J4 R0 X9 V
■ Second pattern channel support
9 S( t5 R6 J+ I7 H) i; Z; B■ Hardware screen rotation |
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發表於 2007-2-6 18:17:18
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