Clock Isolation Logic and Circuit for Complex SoC Designs

chip123

這段英文講的是「時鐘隔離」技術。把時鐘作為資料處理時遇到的問題以及相關的解決方法！
哪位高手能幫忙翻譯一下大意？能有進一步評介、討論分享更好!? :o

Complex SoC designs often implemented various IPs and embedded memories. It is not uncommon that clocks are used as data to qualify signals in IPs, particularly legacy ones, and to switch address and data buses in dual access embedded memories which are popular in low-power designs. Using clock as data has created various issues in timing closure, particularly in logic and physical synthesis. To resolve the issue, a novel clock isolation method has been developed. The principle of the method is to introduce a clock isolation circuit which tracks clock transitions just like a clock signal, yet isolates the clock from the “clock-used-as-data” logic. As the result, clocks will not be part of logic paths and the design becomes “STA-friendly” where all path timing can be checked by synthesis and STA tools in normal ways. The advantages of the method include better quality-of-result of a design, fewer timing closure iterations and less complex design flow. The clock isolation method has been successfully implemented and verified in a complex SoC design.