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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。
% `' k/ }8 a! B7 \4 B0 L//所有註解都要保留
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, s% x3 }) @7 j3 N; C: n7 b`timescale 1 ns / 1 ns
) V' @% X+ F8 E) }( L, G4 j) @ Dmodule xclk(sclk,ena,set,outp);' A& M0 @$ h4 E- h' s
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input sclk,ena;
/ V7 }/ A1 X7 _0 d4 v/ m N( S* kinput [1:0]set;6 o' p2 N$ [8 X3 S7 x! z* D
output outp;
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wire outp;
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2 t! n; M# t1 b" q6 y/**** Node preservation for nodeA **************/ H, C6 p! ]( ]% d2 ]3 i* x. A
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//exemplar attribute nodeA_5 preserve_signal true: Z0 }8 ~: B# w: C1 q5 }9 @' I
, r% [$ ]6 a3 k//exemplar attribute nodeA_4 opt keep+ _6 u0 l3 E5 r6 b% ^4 r
4 Q' P2 |( o' a3 Z) l+ u/**** The following comment form also works ****/
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8 K) `5 B( j3 i: y//exemplar attribute nodeA_3 preserve_signal true
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//exemplar attribute nodeA_3 opt keep$ c7 M# r& E5 j; B
- p4 T6 c, j' A0 P# J9 K/**** The following comment form also works ****/
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//exemplar attribute nodeA_2 preserve_signal true
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; X& u& D% \+ v$ `+ ^6 K! d) f//exemplar attribute nodeA_2 opt keep& s4 t2 N. \# V7 c1 X
5 t- p( o; w" n, o' V/**** The following comment form also works ****/
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//exemplar attribute nodeA_1 preserve_signal true
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//exemplar attribute nodeA_1 opt keep2 M. h9 `( E6 q+ g) L
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/**** The following comment form also works ****/
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/*exemplar attribute nodeA_0 preserve_signal true
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( o+ C: D: }7 d! d# k1 v& X( x* {exemplar attribute nodeA_0 opt keep*/ + l( t% |$ m, E# u+ ]' l1 U
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J5 E E6 N2 i/ Y6 nwire nodeA/* synthesis syn_keep=1 opt="keep"*/;7 {1 S& q" Q4 O: L' q7 S
wire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;' z) H7 d; `1 h0 x& o
wire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;
# G) u! K0 L% Z% E) \5 ~wire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;) Z: f; T) \( {
wire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;3 p0 u, Q' d3 g* q3 k
wire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;0 x X8 ~+ @0 A
& R8 _+ I& i: dassign#1 nodeA_0 = sclk & ena;
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assign#1 nodeA_1 = ~ nodeA_0;
% }0 Q0 i8 @5 |; Tassign#1 nodeA_2 = ~ nodeA_1;5 X8 w t: k: y6 `/ Q; ^$ Y2 x
assign#1 nodeA_3 = ~ nodeA_2;. q! g$ s9 l# p7 H/ L; r4 r
assign#1 nodeA_4 = ~ nodeA_3;
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+ R3 e; s+ l: d: u* N+ X& [3 D( T8 Treg xout;
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, h" |9 I1 B# V& dalways@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)9 C* |; D; ]3 {; G9 L% z3 n6 m! j! i9 F7 A
casez(set)
4 g4 K4 b8 R" d& b( J- ~6 {" u 1: xout =#1 nodeA_2;: \& i3 j. n6 T1 O% R- P
2: xout =#1 nodeA_3;0 c7 {1 D u, |% m/ d' [# E5 }
3: xout =#1 nodeA_4;
! k0 P0 }+ G. D5 b; j default: xout =#1 nodeA_1;
1 t+ I6 z6 v9 T7 `# I endcase0 }5 F& M0 h2 P {3 J4 j2 G* o
; w6 C$ U8 S, ] Fassign#1 nodeA = xout;
8 d) f3 L7 E9 u& [( R( m3 Vassign#1 outp = ena ? nodeA^sclk : 1'bz;# R. J( M) i. ^, M
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' ]6 E- |' p; r1 v' M' D`timescale 1 ns / 1 ns& w! |& m- l( c8 z( o
module xclk_tf();9 |) |. _0 M' G
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// Inputs$ F* e5 L& D; x' p) z i' Y
reg sclk;/ G- \/ f$ ]4 K6 `2 n
reg ena;
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+ M" q# `* S* n- ~ ^+ p4 [// Outputs
1 e, f1 d* C% y wire outp;
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7 J1 {/ y/ H4 k xclk UUT (- X6 V/ p, i& H! Z, |
.sclk(sclk), 5 a! e; u7 v; s0 Q
.ena(ena), 1 ?9 l! I" S3 d6 q8 n
.set(set), / J% D% t+ `0 h7 u7 x0 n( Q
.outp(outp)
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sclk = 0;
! M1 Z8 I9 r" q4 C; ?- } ena = 0;* A8 Z: f3 a7 }# c. T
set = 0;
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always# 5 sclk = !sclk;
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initial begin
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ena = 1;
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set = 2;
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#2000
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1 D! q( s6 P9 b9 I: dendmodule // xclk_tf |
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