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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。
% K: y% {) U9 j/ G" o% ]//所有註解都要保留2 U6 w- m3 X$ m. D1 h s2 ~
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`timescale 1 ns / 1 ns3 Q( U5 |( d& I# @
module xclk(sclk,ena,set,outp);) J" c: q5 s( X
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3 t U7 y6 Q( Tinput sclk,ena;& D; m; D" V, {* ?3 l$ H; L
input [1:0]set;- f$ }( \0 x& h: L8 v! M
output outp;
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0 m' l2 G: e# W6 g9 ^. }" V. H+ U% xwire outp;
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/**** Node preservation for nodeA **************/
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# R; ^& Q& o: N//exemplar attribute nodeA_5 preserve_signal true: X1 D1 P% w9 s, b
0 z6 {( ~6 v# L/ Q: R. D0 r2 _//exemplar attribute nodeA_4 opt keep# [9 S/ W6 r4 ]& T: f" j# X
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/**** The following comment form also works ****/
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//exemplar attribute nodeA_3 preserve_signal true. [. l( A/ Z: z4 }
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//exemplar attribute nodeA_3 opt keep
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/**** The following comment form also works ****/# i( r, `1 o t6 Y$ i7 D
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//exemplar attribute nodeA_2 preserve_signal true
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4 E( s# T' G3 N P, q( u5 `0 f//exemplar attribute nodeA_2 opt keep0 w P; Z+ `: \: O* m( e# A* b
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/**** The following comment form also works ****/$ {0 G3 q: B( u
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//exemplar attribute nodeA_1 preserve_signal true) H+ U0 M' w, W2 W" ~( i
0 [ M0 u' S3 N//exemplar attribute nodeA_1 opt keep# B% [ q5 R$ B
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; }: B8 p$ v M/ g, { ~6 l/**** The following comment form also works ****/5 x+ w) L1 t/ m9 M [ @
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/*exemplar attribute nodeA_0 preserve_signal true
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exemplar attribute nodeA_0 opt keep*/
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wire nodeA/* synthesis syn_keep=1 opt="keep"*/;6 ^9 Q# \& E/ b/ P/ p2 t
wire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;
% l6 K. z4 {) h8 N* }7 v! H& X4 E% {( Vwire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;% x6 T& t* m6 u2 q; H
wire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;
9 i/ m- n- O% x0 I3 hwire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;, @' D# f& C9 v8 _, v( w
wire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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, s/ k3 S, G3 W0 C* z9 uassign#1 nodeA_0 = sclk & ena;5 R1 R) T+ v/ o( V5 c& r& w3 I
0 c( ]; D8 i: M V9 w7 rassign#1 nodeA_1 = ~ nodeA_0;
5 K2 Q2 y% w8 ~8 x3 N' qassign#1 nodeA_2 = ~ nodeA_1;$ O; `+ Q% D" _ v. B" q
assign#1 nodeA_3 = ~ nodeA_2;
: g9 M1 S! ^5 c5 ]" ]5 Vassign#1 nodeA_4 = ~ nodeA_3;3 W$ i' `% l( D* l. i
* {+ v; W( ?* }& lreg xout;
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always@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)6 m4 H C5 @7 d! \4 ^9 B, l
casez(set)! `- D6 X' h* U3 D5 Z1 ^! t+ F
1: xout =#1 nodeA_2;. L8 L+ A6 v0 \# |; ~' k# `
2: xout =#1 nodeA_3;2 c. C* ]* }& E& O) F) y( ^
3: xout =#1 nodeA_4;4 l. J$ x' U7 ?7 P9 k6 S% A
default: xout =#1 nodeA_1;
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" i0 l" m! U% G5 n0 Jassign#1 nodeA = xout;
9 E3 f& v' |. V! jassign#1 outp = ena ? nodeA^sclk : 1'bz;
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, ?' z( a' ?3 W2 i1 _- r`timescale 1 ns / 1 ns% z6 v0 C$ F2 V7 t6 K4 X
module xclk_tf();3 h' Z a& X- R" e. m/ W" L
0 m H, F- A, M! y. P; Y9 ~# M! q// Inputs
T- D: t |8 S5 Y4 E( v! n7 v reg sclk; h, c) ]0 @. S& [! _/ p' u' v6 g
reg ena;3 k8 e$ W8 |" O- v5 Z S
reg [1:0] set;: k- z/ X# t( d+ z& T0 O: J6 z
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// Outputs* o/ B1 d( v; n# p7 q K
wire outp;
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xclk UUT (
1 v$ U6 Q# |, Y8 f( N .sclk(sclk),
2 a+ w/ x* o9 s .ena(ena),
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.outp(outp)0 F+ @, h2 V& v- g4 p! S" A$ Z( t
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initial begin
0 b- @6 C" C2 i& v sclk = 0;
+ {# ?; P9 Q B7 l+ N ena = 0;
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, L3 ^2 {' z9 l2 s" falways# 5 sclk = !sclk;4 F8 A$ z4 a" e& n7 w
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ena = 1;
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set = 2;
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set = 3;
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1 z5 L* s( C5 x+ I $finish;
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7 v, |2 |# A; G; V$ g" cendmodule // xclk_tf |
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