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//可直接透過synthesis tool用於PLD,FPGA不可 LUT delay則要採其他方式。
0 z, \4 T% W- f8 `! x$ c6 J//所有註解都要保留
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3 z* _) C ?0 v) R`timescale 1 ns / 1 ns
- L8 n) y7 q' X. Dmodule xclk(sclk,ena,set,outp);0 F5 W5 T" D t. ~$ O
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input sclk,ena;3 b6 V% F9 K/ A* J0 i% p8 j
input [1:0]set;
2 { L1 `7 M- Z+ Soutput outp;
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5 Y1 x6 H. V' p+ `$ @% u8 N7 | g9 Q4 m8 }wire outp;
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/**** Node preservation for nodeA **************/
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//exemplar attribute nodeA_5 preserve_signal true
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! I9 M3 a4 j/ l9 V! d) _//exemplar attribute nodeA_4 opt keep0 `$ B& y1 F2 T9 W; O6 d
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/**** The following comment form also works ****/
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//exemplar attribute nodeA_3 preserve_signal true
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//exemplar attribute nodeA_3 opt keep
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/**** The following comment form also works ****/6 _! }: l, i& Y2 P
, p5 y! I, d. J//exemplar attribute nodeA_2 preserve_signal true
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1 q$ Z7 N8 X: u6 G//exemplar attribute nodeA_2 opt keep
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/**** The following comment form also works ****/
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//exemplar attribute nodeA_1 preserve_signal true; F; K/ O/ C, G+ ?0 l2 f
, u' K" i" q4 }) c: N8 x9 N//exemplar attribute nodeA_1 opt keep2 E3 z/ z: l7 X# N6 _" Y/ I
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/**** The following comment form also works ****/& | W5 Z6 [; v& M# ]
& E8 ^7 P8 e( _, E3 H# z/*exemplar attribute nodeA_0 preserve_signal true
2 a5 P x& x' y5 d9 N' y w; ]% ^5 F m' ?+ \# K. w$ o
exemplar attribute nodeA_0 opt keep*/
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% N9 q4 j) m. |# D$ M' C |( nwire nodeA/* synthesis syn_keep=1 opt="keep"*/;
1 i% w; q9 i+ O1 ^& e9 awire nodeA_0/* synthesis syn_keep=1 opt="keep"*/;% K7 o2 Z9 M+ h4 q9 g7 u
wire nodeA_1/* synthesis syn_keep=1 opt="keep"*/;% S/ Z7 ^& [5 ^1 K& B2 n% a8 Y/ V
wire nodeA_2/* synthesis syn_keep=1 opt="keep"*/;6 B% C, M1 A/ M# A* m9 `9 |
wire nodeA_3/* synthesis syn_keep=1 opt="keep"*/;
! |- X) G! p4 e$ Y* zwire nodeA_4/* synthesis syn_keep=1 opt="keep"*/;
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8 w# _. f9 d1 ?9 Yassign#1 nodeA_0 = sclk & ena;! U% R! e6 M4 |+ w/ ]" z, C
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assign#1 nodeA_1 = ~ nodeA_0;
, U `% v, X7 | @5 z: r6 `assign#1 nodeA_2 = ~ nodeA_1;
: e, @9 M- E3 Z0 h* i0 nassign#1 nodeA_3 = ~ nodeA_2;
% V3 B7 |) n5 B. `- massign#1 nodeA_4 = ~ nodeA_3;/ `1 n- A" e7 V2 Z4 W
7 I% I! V- B3 v8 O( q/ Lreg xout;
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; Z5 Q7 c: P" s0 ?- X9 i# A) walways@(nodeA_1,nodeA_2,nodeA_3,nodeA_4,set)$ U' Y2 A- X) c
casez(set)" O1 I+ O# r6 b+ \/ [
1: xout =#1 nodeA_2;$ D2 c$ E2 v. J" Z' [
2: xout =#1 nodeA_3;! U) l+ J# x2 n0 x
3: xout =#1 nodeA_4;
0 V2 n3 r2 G; G I9 l default: xout =#1 nodeA_1;: M, k, r/ J( J7 z8 ^4 R. B
endcase
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4 ]1 w5 T) o* D' c; j2 \; ^! w8 h: Vassign#1 nodeA = xout;
, S- E( p m& wassign#1 outp = ena ? nodeA^sclk : 1'bz;" p5 \* h9 B; ? l. |* e; L
$ w) d% l+ W6 W8 X5 A5 Lendmodule' Y3 i4 W0 I3 g: w+ D4 |1 ]
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/ V/ |" y/ t h& q`timescale 1 ns / 1 ns: P+ o2 k- B! T- O" C6 [! O& e
module xclk_tf();6 X; R" I& ~5 A8 h* w4 M" ^( J
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// Inputs% y J/ Y, }1 \! X# b
reg sclk;
. H& P/ i6 E9 W* n6 }6 {7 C' f reg ena;* @3 K8 g: c k+ o9 D1 L2 i
reg [1:0] set;
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// Outputs) E4 ^% c6 N/ @4 ~# K# y
wire outp;
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xclk UUT (
$ @0 U5 L8 Y' F; W .sclk(sclk),
; c4 \) O0 c" d8 C0 ]! J .ena(ena), 0 M. h- X' i, {6 w8 Q) J+ {
.set(set),
( X+ _ K- s) [5 L .outp(outp)
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initial begin* H$ K+ V# [4 \2 I& N
sclk = 0;
7 Y8 \# b/ y+ h5 ~5 ?! G' y ena = 0;
* L* I' k; k5 H set = 0;
3 b, u3 P5 G: G4 h) N- Z7 T' g end
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always# 5 sclk = !sclk;
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4 J w. ]1 L. ~initial begin/ ]- y4 g( `5 L# Y1 v1 c
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ena = 1;
2 Q8 U& N, M9 R. J% W #2000 : l+ a9 F8 C3 C; o) ?
set = 2;
* ^- q; m5 e, {; R; D6 d #2000
4 N+ G, L4 Y: a/ \9 `2 ? set = 3;! W1 F" C# J' K$ o# `
#2000
6 l) [# w3 h% F% m0 W. k% c& O% J $finish;
6 r& O9 z% |; c2 Iend
* Q6 Y; _$ `' C1 L, kendmodule // xclk_tf |
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