用傳輸門VCO和動態PFD設計低功耗CMOS瑣相環[簡]

sjhor

A CMOS Low Power PLL Designed in Transistor Level with Transmission Gate VCO and Dynamic PFD
YUAN Shou-cai,ZHENGYue-ming
School of Electronics and Inf ormation Engineering,Xi’an J iaotong University,Xi’an 7 1 0 04 9 ,China
' P* p6 p7 |7 [3 fAbstract: To realize the high speed and low power CMOS PLL (Phase Locked Loop), the new circuits of VCO and PFD is designed in transistor level. In the VCO , the high speed and low power is realized using transmission-gate(TG ) with an adaptive delay cell and low supply sensitivity. This delay cell has a built  in compensation circuit that senses and corrects the delay variation caused by supply fluctuation . And in the PFD , low power and small chip area is realized with the dynamic inverter. A fully CMOS PLL using these components has been designed based 0.6 μm CMOS technology and its SPICE model. SPICE simulation results show that at 2.5V supply voltage, the designed PLL can operate over 1000MHz and dissipate power less than 50mW .

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howard355021

看摘要寫的蠻不錯唷 ！！不知這是幾年份的PAPER，希望這篇對小弟有所助益

new20062007

感謝大大分享呢
這個對我很有幫助

930709

感謝你大大分享
3 f: H, I2 R) ~, [. |6 K, Y受益良多

yh529

感谢大大分享，学习学习

kevin20833

剛好正在收集相關資料。謝謝你的分享.非常感謝!!!

eli0717

真的是好東西，我想好好讀讀這些寶貴的文章，學習上遇到大困擾啦！

laasong

同樣做PLL的來看看囉  希望多學到東西

skygardon

剛入門學習電路設計，多謝分享這么好的資料哈，好好研究學習一下！

zorro

最近正好在學習PLL，希望自己的等級能够把文檔當下來，感謝大大的分享！

hero230

最近看一篇paper有用到pfd~
- G4 L' p8 `7 d" X1 U8 o, u/ A有點不了解它的動作~
6 ?1 a5 g9 }% X* ?% `* {希望有幫助~
謝謝

guweiru

我還是菜鳥~正剛好剛好在學ㄟ~
6 f3 U! o( a' C' `! t0 {希望有所幫助!!!!!!!!!感謝囉~

averyer

正好需要用到~來參考看看囉~謝謝啦~

anita66

好東西,不過看起來是簡體字,還是原文比較不會"失真",3Q~

timelj

先顶一下，哎，真的好需要些资料啊，希望写的很详细，

lianlianmao3

Thank you very much Thank you very much

yoyo20701

真不錯耶~~~好東西~~小弟最近~~~~想去做看看~~~謝謝

elfmushroom

最近在找有關PFD的資料，希望這篇能有所幫助啦
" d* h& n( X5 u7 Z. M: U, x1 B  L謝謝分享。

kevin

Thank you for sharing this materials

yhchang

感謝樓主大大的分享
希望這篇文章能夠對我工作有所幫助