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It’s common knowledge that the verification
( {9 x, N5 q Nstage for a given system is; T2 }3 P9 }! ]0 Z5 U3 J) F( j6 C
around 70% of the overall design' C9 q7 I$ A1 Y) ]. _
effort and schedule time. Reducing8 |" g1 B% V; F2 o) u) k
overall time spent in test creation and6 f4 k3 e) [7 m3 S* Y: V
design verification is a high priority.
$ G0 U) p8 @9 ?Success in these two areas increases4 f+ K; h) e! l# I+ ]
productivity and helps deliver products$ W3 R# P2 l* x! r' z: a, l: ^
to market faster. To achieve these verification
1 b1 G7 N. ^7 C' D9 Q) Cgoals, engineers are constantly
/ k/ k2 Y: Z3 ?. xlooking for new and innovative ways to) v8 }- Y. u) o& P
conquer the verification challenges that. Y2 P+ C+ [, l
face them.0 @( q/ R5 l" v- `3 z
This article discusses a layered verification/ m1 m# r: _9 |1 ]) G" q
approach as applied to an AMBAbased
" F* ?: K v" [8 Ksystem component. The layered- j8 X2 O* }8 @: W: l4 `
approach is used to create a standardized
' P. a# C7 V. a1 _verification environment that can
* D9 L" X; E* Eadapt as the design challenges; V& k9 ]+ `( e$ H* o$ g8 s
increase. Typically, reuse is very high
8 r H+ ]/ a9 M0 _within an AMBA-based system because
, ]' Y( L# o5 f3 y$ ]many new designs are based on earlier
- _7 q% z$ c% Q Z& Tversions of the standard system. The5 w% M! N0 H5 f( G! o, j H+ H: ?
example shows the layered approach" r1 ?8 d, I( F0 k& y, N+ D& B; z( U
being applied to verify an individual2 A+ o5 a% u" Z# b! v
block as well as its integration into the* U* V* ]& R5 I- Y
subsystem and final system representation. |
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