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AMD Geode LX 800@0.9W處理器
General Features
" H p. N! i$ i& ?" e■ Functional blocks include:
6 W- l& s1 ?3 i) E( I— CPU Core
' Q: N8 |, G/ ` S6 }— GeodeLink™ Control Processor! j. q" _. a$ U5 G4 H
— GeodeLink Interface Units9 {0 `3 y* c2 l; L. Q
— GeodeLink Memory Controller! f' N& K2 r/ H; x$ \2 `* e
— Graphics Processor( v4 P9 S+ \' g' j; b
— Display Controller p; |- @7 d- C0 x
— Video Processor
7 M4 O2 X3 ]4 H7 u# L& j' H– TFT Controller/Video Output Port
# b7 C! I; y( ?— Video Input Port( W, v( h1 _- l9 x% @
— GeodeLink PCI Bridge$ W+ {! Y/ A5 N3 Y/ D
— Security Block
) L& T9 t' |7 J9 c1 u■ 0.13 micron process5 t$ {2 v6 I: T- Y& C' N( i( i: I
■ Packaging:
$ k" S' H$ a7 i5 r" [— 481-Terminal BGU (Ball Grid Array Cavity Up) with3 z1 D% r; f8 u0 B) h
internal heatspreader' A$ b1 K$ ~( W+ n
■ Single packaging option supports all features
0 \, e! {; M [ t. ]1 X3 ?6 U6 l5 u# fCPU Processor Features/ s- L1 w: _4 Q
■ x86/x87-compatible CPU core
: h8 q4 o9 s, E: t$ E■ Performance:: L4 y* ]* S! h' H& x/ b1 O
— Processor frequency: up to 500 MHz
" U: q- X" S6 L, h' g— Dhrystone 2.1 MIPs: 150 to 450
8 m7 `: @- ?1 K* }— Fully pipelined FPU' G8 ]% {2 |' o
■ Split I/D cache/TLB (Translation Look-aside Buffer):
: t }9 `9 @& y6 u# w— 64 KB I-cache/64 KB D-cache) J- p8 J9 |; x- I- B
— 128 KB L2 cache configurable as I-cache, D-cache,* r& z0 f1 m) y+ w4 G) S( S
or both0 N% u8 D. {$ b4 Y/ y Q# q. q8 m9 I( S
■ Efficient prefetch and branch prediction* n9 H4 G, N$ ^. @
■ Integrated FPU that supports the MMX® and! ?# Q1 p7 ?# P) ~5 w9 N. S
AMD 3DNow!™ instruction sets5 v' y2 t/ O; U$ h; |5 g" J; Q' K
■ Fully pipelined single precision FPU hardware with; t! c, g7 m7 g3 G* @2 Y4 z
microcode support for higher precisions& e. T+ z3 G! X, L
GeodeLink™ Control Processor y# m8 G' k$ u6 ^2 H
■ JTAG interface:: S: e1 z0 c6 J
— ATPG, Full Scan, BIST on all arrays; X5 s. [- h" M7 s# d: K! ^
— 1149.1 Boundary Scan compliant
* w* t1 S5 u) e7 d% w■ ICE (in-circuit emulator) interface
7 X% m. m$ d5 k b b$ w■ Reset and clock control! P. { {6 U7 D' n
■ Designed for improved software debug methods and: l2 \: v1 E s
performance analysis9 J; M& ~3 I$ P( r$ [$ _# F
■ Power Management:
$ Y R$ _3 M3 C+ w— Total Dissipated Power (TDP) 3.8W, 1.6W typical @& T: A! I( l( F P2 o
500 MHz max power
1 f( _5 F5 r& `6 J" u— GeodeLink active hardware power management
: `& N+ [8 D7 M" t h% V— Hardware support for standard ACPI software power
) K* S! ?" o! U* lmanagement
; z7 ]( v0 @" l— I/O companion SUSP/SUSPA power controls
( ]& Y( C% A, E& u! Z— Lower power I/O
6 A' N+ J4 ~# t, `' { T— Wakeup on SMI/INTR
; _. A6 H7 y4 I- y6 q" }9 R Z' r- a■ Designed to work in conjunction with the
) z! t4 p9 T3 M* ~: U5 V3 uAMD Geode™ CS5536 companion device
$ d" l v" L7 M% HGeodeLink™ Architecture! L9 O7 S- y+ h+ ~
■ High bandwidth packetized uni-directional bus for" N, L K) O& o) p4 N
internal peripherals3 C* N, X# @( l0 a) J
■ Standardized protocol to allow variants of products to be
/ v3 J6 ]- I! P8 [3 N; [9 |* Z6 Odeveloped by adding or removing modules
2 d6 p( z V! \' R" B, I■ GeodeLink Control Processor (GLCP) for diagnostics. F9 g8 S* d% n' N
and scan control
: T) Y( J; ]+ l7 K■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
( Z; j, |0 ^$ n6 }2 p. q% b4 AGeodeLink™ Memory Controller
" G# H6 d0 d4 ?$ N6 ^# j+ I; N! E: i" o■ Integrated memory controller for low latency to CPU and$ F4 l( e+ M9 w6 A, r) T6 g
on-chip peripherals( w* m7 p: L' q/ y, o
■ 64-bit wide DDR SDRAM bus operating frequency:
# p& p: T3 t$ [+ A1 N& z! L0 [8 s— 200 MHz, 400 MT/S
* H" T1 i' e1 s# R■ Supports unbuffered DDR DIMMS using up to 1 GB: U% f- `+ a" ] ~4 b
DRAM technology
. W8 b$ [6 o, J8 p6 Q- V4 j) D■ Supports up to 2 DIMMS (16 devices max), C1 n3 d- i9 l3 y" `: @
2D Graphics Processor' \ u) g* B+ x8 } p
■ High performance 2D graphics controller) Z: h1 Q2 {$ \2 D5 F1 T* Y, X
■ Alpha BLT
6 p/ ?% e- A) a. M. {% l0 h■ Microsoft® Windows® GDI GUI acceleration:
4 [& L, B# F4 `; O; O+ X. e) t2 i— Hardware support for all Microsoft RDP codes
" H; T6 A6 c% W( |) u, i4 N■ Command buffer interface for asynchronous BLTs
, V& A' `- M8 P■ Second pattern channel support/ G/ W% Y1 t e- _3 J; l- z
■ Hardware screen rotation |
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