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AMD Geode LX 800@0.9W處理器
General Features
/ V( g M4 P) d7 F+ t1 L■ Functional blocks include:/ o; e. c2 r/ f, p+ h! a
— CPU Core$ d2 M& s! V& U* A7 v/ J
— GeodeLink™ Control Processor
; e+ f K: O, V8 m( @9 J— GeodeLink Interface Units
4 m2 `! K; n9 ~8 K— GeodeLink Memory Controller- c j( O2 U* m+ \
— Graphics Processor$ @5 f$ [& U8 \6 ?8 s4 ~7 e/ \+ x
— Display Controller
y- @4 I1 B" r/ \2 E E— Video Processor8 m) U n; _: H
– TFT Controller/Video Output Port8 |6 Y, O/ g: h3 D M4 G9 o
— Video Input Port
/ ]3 K5 P% \1 a) U' p$ A— GeodeLink PCI Bridge5 d. C4 A3 F1 N2 X
— Security Block
' H' t. ] K% U" J( t■ 0.13 micron process
0 N* x' z! C' j6 W% q% @5 v2 \■ Packaging:0 O3 Y$ O& W' s3 M$ y; k
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
1 ~4 n& M: V5 M/ C; O0 O) L5 N; s3 _internal heatspreader
, u6 O/ i% m+ r, B■ Single packaging option supports all features7 u& C9 s& \8 C/ ?: m/ f( Z) m
CPU Processor Features
( X4 ? b( o7 s5 S■ x86/x87-compatible CPU core
0 q' H% a$ _2 Y7 \$ ?8 n ^■ Performance:1 \$ Z9 C* E" ~5 ^% q8 s3 n
— Processor frequency: up to 500 MHz
; G8 F5 F; i/ {7 C8 X- X6 { p, S— Dhrystone 2.1 MIPs: 150 to 450
( B! X$ E, z5 t9 u/ G }; |— Fully pipelined FPU$ r, ~1 e8 E6 `" t& V# y
■ Split I/D cache/TLB (Translation Look-aside Buffer):
% }# }6 u, W# Z% O) D# r— 64 KB I-cache/64 KB D-cache, T5 w5 ~2 U& o
— 128 KB L2 cache configurable as I-cache, D-cache,( H. ]" y- y1 O$ w* e
or both4 t- M& u# B! Z+ m/ r
■ Efficient prefetch and branch prediction) }" @- r) r8 F/ k! m' n7 B1 o
■ Integrated FPU that supports the MMX® and
$ m; c" l8 E" M4 `4 oAMD 3DNow!™ instruction sets
$ J6 j/ X; p/ F■ Fully pipelined single precision FPU hardware with3 ~) w5 X% Y, Y9 f: R
microcode support for higher precisions9 W6 H2 ^2 F" o
GeodeLink™ Control Processor
6 k. }* k9 y8 Z4 f/ N& W" x( \! k■ JTAG interface:3 m+ A" i( \5 _
— ATPG, Full Scan, BIST on all arrays
1 J9 Y4 V( d( x- [( \" Y! \— 1149.1 Boundary Scan compliant
4 Z( o) U) W9 D5 N■ ICE (in-circuit emulator) interface
0 K8 ?$ n" p3 d" q* s■ Reset and clock control% z7 m$ O1 j% Z! ~
■ Designed for improved software debug methods and* H3 {$ X* l+ q! r Y
performance analysis* T) b ^$ N+ A& a; I& s- y7 H
■ Power Management:' r9 W8 B$ `/ S, R
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @, w4 Y1 h% [/ {+ {* l
500 MHz max power! S# a" A% I2 `7 }/ B) f& O! K
— GeodeLink active hardware power management3 u9 I) G' I E# \' {/ [5 `
— Hardware support for standard ACPI software power
) A9 w) }$ @: F7 Pmanagement( o: V/ d3 R- ]; y9 w! E2 A0 | w
— I/O companion SUSP/SUSPA power controls( [% ?6 _4 v( `% D$ D
— Lower power I/O
& l6 Y3 W$ w% |. r: L A1 ~7 I— Wakeup on SMI/INTR" n+ \' ?! S* y* S" _8 Q
■ Designed to work in conjunction with the/ c8 ~: u6 Y8 ^, z" ]* M5 S
AMD Geode™ CS5536 companion device- r/ h$ r6 P: R. l6 V
GeodeLink™ Architecture r8 m$ k" U) O: m. A1 V! N
■ High bandwidth packetized uni-directional bus for' e; B1 ]7 y* E& P N. D
internal peripherals
8 D, n, I/ S" _2 d! H■ Standardized protocol to allow variants of products to be
- i8 I" Z& B, \6 Odeveloped by adding or removing modules3 ]8 r5 h# y' ~4 o/ v
■ GeodeLink Control Processor (GLCP) for diagnostics$ ]7 z& Y7 X9 }6 v1 B
and scan control
$ q5 b' v+ N2 {* B3 [# ] r■ Dual GeodeLink Interface Units (GLIUs) for device interconnect. F; {1 c( G. w% O \
GeodeLink™ Memory Controller. \( |9 E6 U d5 W
■ Integrated memory controller for low latency to CPU and3 d) t3 X W, n3 b, m
on-chip peripherals" s: V6 W0 U1 K- l9 H& `) n
■ 64-bit wide DDR SDRAM bus operating frequency:" ] H$ g' X3 M/ r) r
— 200 MHz, 400 MT/S
- V* A g! D r6 E6 O" G■ Supports unbuffered DDR DIMMS using up to 1 GB
+ h/ r: o1 V$ S# X# L* ?7 lDRAM technology. n$ x5 S F/ s) P7 ]4 f
■ Supports up to 2 DIMMS (16 devices max)
& a2 n, n: _2 m' J2 a6 d. x2D Graphics Processor- [1 V/ f7 O& O+ b; X
■ High performance 2D graphics controller' S* Y, A& I) V m9 E0 t" H( ^$ E
■ Alpha BLT
* r1 X$ \% R6 c) F■ Microsoft® Windows® GDI GUI acceleration:! U, n7 U+ x! j) x
— Hardware support for all Microsoft RDP codes
; w1 f# C5 e* _) b9 `% K( a0 s1 ]■ Command buffer interface for asynchronous BLTs
8 U6 E( L$ f. ~2 L) ~7 G- k$ y■ Second pattern channel support8 D4 l9 P+ u* s2 [
■ Hardware screen rotation |
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