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請問一下,有人可以幫我看看Verliog問題出在哪嗎? 畫面異常啊!!
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module vga_ctrl(clk, rst, R_in, G_in, B_in, oRequest, oVGA_H_SYNC, oVGA_V_SYNC, oVGA_SYNC, oVGA_BLANK, oVGA_CLOCK, oVGA_R, oVGA_G, oVGA_B);" Q& X6 i, z$ t8 n* q7 A; h; A
input clk;- n. u) T* }% n5 k. T) _3 _& n7 p$ z
input rst;
6 O. _. l, O' D# W input [7:0] R_in;
# k( i- N& _( I* k# c$ Q input [7:0] G_in;7 ^) E8 Q# S% l4 Y3 K! \6 v
input [7:0] B_in;
" ^1 K% ^4 s3 S output oRequest;2 r3 v! M9 S; ?" t3 e/ E7 {# L
output oVGA_H_SYNC;
8 F z3 z! {3 t2 N# y9 { d. ] output oVGA_V_SYNC;* v( c- X; a; N
output oVGA_SYNC;
" v1 C5 j$ C3 j) f( s5 ^' f5 g7 H9 Y output oVGA_BLANK;
$ ^! U1 E" |0 l8 H9 K output oVGA_CLOCK;2 x1 x7 {* N+ s0 j0 m8 ?% D
output [7:0] oVGA_R;
1 a! k2 F' X1 t( n8 O6 ~& ^+ p& L/ u output [7:0] oVGA_G;1 s) \; Q2 t# V! F3 Y
output [7:0] oVGA_B;
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# S3 B4 s e2 @9 o% e3 G reg oVGA_H_SYNC,oVGA_V_SYNC;' }9 |- G. m+ `/ u, m0 T
reg oRequest;, {! ], Q Q. U4 L9 r
reg oVGA_SYNC;8 b1 W5 c) |* |4 m3 |
reg [7:0] oVGA_R;
9 q5 z$ }) F$ t! Y, |7 n reg [7:0] oVGA_G;- {! I# @/ |: d( [
reg [7:0] oVGA_B;, |+ v# l8 y( T4 K# @# v' S
$ G2 {) t: ]- U. x$ j, F, S% B parameter LENGHT = 1024;
$ L1 B+ a) n2 `. N parameter CNT_SIZE = clogb2(LENGHT);
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`include "VGA_Param.h"
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reg [CNT_SIZE - 1:0] h_cnt,v_cnt;( K$ }1 C, H/ z+ }
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always @(posedge clk)
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if (rst) begin
2 I' S+ G# g8 } D7 N/ j; h) t+ Z oVGA_R <= 8'd0;) y6 z! |0 G, k6 ?# J* N+ `
oVGA_G <= 8'd0;
* y& K) C8 `( V: n$ q* ]. h4 }0 w oVGA_B <= 8'd0;
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else if(h_cnt>=(X_START-1) && h_cnt<(X_START+H_SYNC_ACT-1) && v_cnt>=Y_START && v_cnt<Y_START+V_SYNC_ACT) begin
j) l4 e* Y1 _( H8 u! N/ o$ O oVGA_R <= R_in;9 W2 k! c: y; s
oVGA_G <= G_in;
# W3 A' V1 P. P3 i6 H, r oVGA_B <= B_in;
8 B, y9 ?4 T' C6 T! h end
' d2 `# x' C: ?# k* o* w" D1 c else begin
# X# L9 P; y9 N2 B+ `, Q' l oVGA_R <= 8'd0;
- `0 d* q6 a5 B! L oVGA_G <= 8'd0;) g1 M; ^" N' k0 M- |
oVGA_B <= 8'd0;# l+ S/ I2 `. n$ z2 x6 \; C/ ]% [
end
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assign oVGA_R = (h_cnt>=X_START && h_cnt<X_START+H_SYNC_ACT && v_cnt>=Y_START && v_cnt<Y_START+V_SYNC_ACT) ? R_in : 10'd0;3 W8 a3 u, z& j, t8 l; T7 ]; J3 Y& k
assign oVGA_G = (h_cnt>=X_START && h_cnt<X_START+H_SYNC_ACT && v_cnt>=Y_START && v_cnt<Y_START+V_SYNC_ACT) ? G_in : 10'd0;( }) D0 U' Y6 ~% T* T
assign oVGA_B = (h_cnt>=X_START && h_cnt<X_START+H_SYNC_ACT && v_cnt>=Y_START && v_cnt<Y_START+V_SYNC_ACT) ? B_in : 10'd0;
7 P+ M- W. ?" N- r3 Nassign oVGA_CLOCK = ~ clk; |
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