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AMD Geode LX 800@0.9W處理器
General Features$ N! B. ]4 G% Y
■ Functional blocks include:
1 `8 ~2 x7 Q/ P3 Y* h( S' A j— CPU Core8 ]2 {( `& }0 l( A$ r1 a' ~: o
— GeodeLink™ Control Processor; B3 I: s8 ^/ {
— GeodeLink Interface Units; p5 t" `# F1 M1 b" o3 I' q5 q% f
— GeodeLink Memory Controller7 B) B0 |' W" S1 O5 L) j
— Graphics Processor
/ F6 }. r0 P" [" v) ~/ ?1 u— Display Controller
O% Q; I7 y/ J1 w t! c— Video Processor, P9 T: r+ I/ c' {# a" l
– TFT Controller/Video Output Port$ R% g& t1 l# c! ~" l3 |) O
— Video Input Port5 e: k" a$ @3 J
— GeodeLink PCI Bridge& R) M' W/ j; x2 h/ Y; K
— Security Block( B* ~& d) `+ Y. _
■ 0.13 micron process# S7 A. x6 ~3 F9 c9 K; E# [& B
■ Packaging:. q/ g; }( P F; `: d
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
# U5 X3 c5 b8 a, Cinternal heatspreader
- [9 r7 n7 j- p6 Z2 \■ Single packaging option supports all features
' I6 l5 y' W5 A" HCPU Processor Features
" c2 z+ b, o# p* r! }& ]■ x86/x87-compatible CPU core/ J6 V F( _9 {2 w; O0 y# Y7 |6 p
■ Performance:
- \3 y0 w0 ^5 E— Processor frequency: up to 500 MHz
. r) o4 b$ k0 y# f/ r# _1 E$ b W— Dhrystone 2.1 MIPs: 150 to 450
( n, ?1 ~8 h s1 s( [( I# E9 u— Fully pipelined FPU
' n1 S9 H( K' p" W■ Split I/D cache/TLB (Translation Look-aside Buffer):0 C, |! R1 i6 D8 m2 \. ~
— 64 KB I-cache/64 KB D-cache
0 V" X8 {9 ^* v6 b( s— 128 KB L2 cache configurable as I-cache, D-cache,0 x: |, O; P( O
or both
4 ^ G- n1 J r9 q2 ?+ q, o( ^, w- h* u■ Efficient prefetch and branch prediction: o4 O6 X8 ~. g1 N3 F
■ Integrated FPU that supports the MMX® and9 `( E3 S o; b$ M. H% A3 n# G
AMD 3DNow!™ instruction sets
8 v0 v% H8 l' k9 z# A■ Fully pipelined single precision FPU hardware with
5 j; s6 t3 [" P7 ~/ b. gmicrocode support for higher precisions6 f# `6 M6 P, w# Q/ ^! Z1 X
GeodeLink™ Control Processor
) b! }; ?: k `0 k3 B2 J8 G, H■ JTAG interface:) Z! l4 U. ~) [/ t
— ATPG, Full Scan, BIST on all arrays
y9 r& I) M" f, f, L— 1149.1 Boundary Scan compliant
( [2 N# b' j" A, ?7 m■ ICE (in-circuit emulator) interface
1 W/ H5 g- d u9 E8 h4 t■ Reset and clock control
- p m' R( y. c4 d■ Designed for improved software debug methods and- H0 H, ^' n6 m3 R% e
performance analysis& u6 v( {5 v) H; i7 S& H8 d; e
■ Power Management:
6 U" f2 ^% z3 ?* o— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
7 ^/ W8 Q% A" {; x1 ?- @500 MHz max power
! b4 x5 {" Z- o! ~# r/ x6 x— GeodeLink active hardware power management
) h M+ B3 r$ c4 N— Hardware support for standard ACPI software power7 l; t2 h0 I! v: @' f( ]4 @
management
! J( J( w/ c0 J5 j— I/O companion SUSP/SUSPA power controls8 L: h4 Y5 K w! ~$ I+ I7 c
— Lower power I/O
- g( R" I) H0 R9 x— Wakeup on SMI/INTR
! y2 y4 O: }1 I1 X3 T; e% f) [* ]■ Designed to work in conjunction with the
& H7 l! g+ z @0 [/ I8 I8 lAMD Geode™ CS5536 companion device3 X. F* Q& t! [" H0 P/ N6 m& r% T
GeodeLink™ Architecture- R# T9 }5 ^( I, j+ h7 U# E
■ High bandwidth packetized uni-directional bus for2 _. D( u( c0 K* _
internal peripherals1 o, N* W+ z) j/ J# `
■ Standardized protocol to allow variants of products to be
+ F0 X w! H$ m+ o# d" qdeveloped by adding or removing modules, ?8 r1 b& d( ? m
■ GeodeLink Control Processor (GLCP) for diagnostics
# T) r( u& I: m% M! @4 dand scan control* X+ W) g$ h/ n1 F! ], k
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
. m! Z; `5 }1 ?, eGeodeLink™ Memory Controller$ `9 j6 M& v+ ^4 W8 H
■ Integrated memory controller for low latency to CPU and; B( k& g% g5 G7 a
on-chip peripherals: x. I6 ~* o, x
■ 64-bit wide DDR SDRAM bus operating frequency:2 R0 Q' r h2 ~5 x; Z, x
— 200 MHz, 400 MT/S1 ]/ u' l* l# x) O: ?1 A# u. }
■ Supports unbuffered DDR DIMMS using up to 1 GB2 i; r1 d6 m8 v9 S3 g
DRAM technology
' d) N1 @/ P' E/ x■ Supports up to 2 DIMMS (16 devices max)4 l' h% ]/ G, j9 M& S# L; [- ^* a
2D Graphics Processor/ ?* \' f- a7 S- i
■ High performance 2D graphics controller
8 f9 R% J7 N* i y) `■ Alpha BLT
4 m8 B6 L! G6 S& V; c4 ^* E/ i■ Microsoft® Windows® GDI GUI acceleration:
2 b6 S; O. N4 m3 n— Hardware support for all Microsoft RDP codes
" B2 g' ?7 S7 U U2 C■ Command buffer interface for asynchronous BLTs9 W$ F! [8 q' O+ h
■ Second pattern channel support
2 h& o0 o P! s$ z$ P■ Hardware screen rotation |
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