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AMD Geode LX 800@0.9W處理器
General Features
5 |2 H: |/ ?, n$ x* s1 s, v& P1 i* K# s■ Functional blocks include:7 P4 e) o4 I' Q7 _1 G% ~" n( E+ Q
— CPU Core
2 b$ g# t5 _& B) }— GeodeLink™ Control Processor0 |( P4 w! v% N% \6 H4 [" {
— GeodeLink Interface Units8 u0 j- `- g& ?# R& I3 Z, F
— GeodeLink Memory Controller4 O9 T# K! r0 F* v
— Graphics Processor
( V# x) [$ b9 W— Display Controller& T. X% p Y: [ k: N; [
— Video Processor s$ ~& {1 ]/ s8 w5 y
– TFT Controller/Video Output Port
f# o2 s( s+ M& k! M- D J ?— Video Input Port
% @7 G2 B# \) D- l! B- V— GeodeLink PCI Bridge7 l( c3 C" ^ i
— Security Block
( D6 z' v+ f+ Y+ W/ \■ 0.13 micron process
1 E* b, H. [5 e# B2 _- g }■ Packaging:; v ]& a6 z$ D0 @7 S/ A, F
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
) o+ x" k3 E( j( t1 Uinternal heatspreader
9 z1 w3 G, G8 D! r■ Single packaging option supports all features
$ V V8 B! z. k. m, ZCPU Processor Features
' R, L; c$ L. X) T■ x86/x87-compatible CPU core
2 n0 i+ W' q% b■ Performance:
0 X2 z& _1 q# X5 ?3 [7 V1 f8 M9 Z/ |" E— Processor frequency: up to 500 MHz) b M" s4 p4 b, `) B- _" {- \
— Dhrystone 2.1 MIPs: 150 to 450
1 O9 L2 e' x. |' f" y* u— Fully pipelined FPU5 y0 A9 a; w/ w$ G3 N# c, i
■ Split I/D cache/TLB (Translation Look-aside Buffer):& O- w4 ^4 d$ j L
— 64 KB I-cache/64 KB D-cache8 _0 M7 N6 B3 u- S4 |
— 128 KB L2 cache configurable as I-cache, D-cache,
' q9 ~5 U0 j: y7 K. Xor both
) _9 s0 W% f! t5 U■ Efficient prefetch and branch prediction: P. s8 S: E. ]. {1 ]0 H! c- P( z
■ Integrated FPU that supports the MMX® and
5 Z2 h1 G5 C# N* J7 K- ^AMD 3DNow!™ instruction sets$ }% k* z, _" Z
■ Fully pipelined single precision FPU hardware with1 `, y# T" J* L) x1 c4 B4 v4 v
microcode support for higher precisions" H4 o. m1 m5 E
GeodeLink™ Control Processor
. U. h. o% l$ M# w■ JTAG interface:/ h9 ~& H; Z" @$ ]- \9 c
— ATPG, Full Scan, BIST on all arrays
9 |8 f# Z, n. K. m— 1149.1 Boundary Scan compliant- W9 S3 p6 u( E8 Q0 [7 O
■ ICE (in-circuit emulator) interface
' f1 P7 t4 ]$ O5 H4 g7 j3 n& O■ Reset and clock control# X8 O2 ?! d8 \ ?$ O
■ Designed for improved software debug methods and. x$ L8 X7 I1 d7 O, ?% D L
performance analysis
6 K7 p4 o [' ?2 k9 J3 }■ Power Management:# p& |' N8 r N8 P* @2 _: N6 w
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @2 L4 X. u2 e: [+ j& U& F
500 MHz max power
8 h1 G" a# c: J3 z: y— GeodeLink active hardware power management
8 L. w9 Z/ E2 g% d/ x4 I8 n— Hardware support for standard ACPI software power4 T; v& s' w/ x: H& s( l
management
& Q/ T% p0 a, }4 }4 m4 B! F# F8 R— I/O companion SUSP/SUSPA power controls
3 A2 i& p( ?# M! [8 \) n# [— Lower power I/O
9 v$ I `# n& A" e: t2 n+ ^— Wakeup on SMI/INTR
" z5 Y+ w7 ^6 w$ o0 T3 i■ Designed to work in conjunction with the8 b. G2 D* q: w
AMD Geode™ CS5536 companion device
9 T) Z4 m: \% t2 f) vGeodeLink™ Architecture% j7 @& p) L' @3 p; p
■ High bandwidth packetized uni-directional bus for
6 j/ [+ B- h- Q% \% Pinternal peripherals J. Q+ C3 j! l, O. R
■ Standardized protocol to allow variants of products to be
; N9 Y3 s6 y8 L0 ]developed by adding or removing modules ~9 k5 \$ V6 _+ [( n: X8 C4 d
■ GeodeLink Control Processor (GLCP) for diagnostics
! [% o" c& T( x5 w t& w' fand scan control/ n9 v8 K% h2 a& s5 D8 o+ [# z/ x
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
! K; W3 Q9 C' Y2 @- ^GeodeLink™ Memory Controller- l1 y9 `: ]3 d4 A5 m4 R0 @' a
■ Integrated memory controller for low latency to CPU and9 O! r" S% p6 y ]
on-chip peripherals. H: G9 c- O! O2 a
■ 64-bit wide DDR SDRAM bus operating frequency:
% X! d* j U; x* ?3 T8 z— 200 MHz, 400 MT/S
s: ^! h+ h7 x" W■ Supports unbuffered DDR DIMMS using up to 1 GB
9 j. y% \, L. g0 |DRAM technology1 e1 J" Q/ u" V, P% ], M; N
■ Supports up to 2 DIMMS (16 devices max); n/ M, x" p8 ~' h8 e6 ~, h0 Q
2D Graphics Processor2 H# J. ~ q; i! A4 @0 D
■ High performance 2D graphics controller
3 t$ E+ ~) ]5 Y, m, e■ Alpha BLT# z2 ^! M7 t5 c9 ~- h
■ Microsoft® Windows® GDI GUI acceleration:
$ G) t: }* G: B. Z— Hardware support for all Microsoft RDP codes4 i/ ~) ?- y, b% \7 ]9 u
■ Command buffer interface for asynchronous BLTs
8 n% D0 w, B/ U1 d5 M% D■ Second pattern channel support
* j6 s5 \" E: {5 N9 |6 E% n4 z o■ Hardware screen rotation |
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