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AMD Geode LX 800@0.9W處理器
General Features
6 k) e* r8 w0 F& s9 {■ Functional blocks include:
$ P9 U( y- c$ Y' u6 r- ]7 G— CPU Core
- d# l6 s8 @% ?- d' N- {— GeodeLink™ Control Processor$ O) V$ X) Q+ q2 O+ b h, L- K+ ^
— GeodeLink Interface Units* b! D0 A6 b: V' h
— GeodeLink Memory Controller
" ?2 K$ Q; r2 q& {7 \% k: W2 J— Graphics Processor) P# k! K, H; @8 O m
— Display Controller
5 \' S. S l+ G" o7 l— Video Processor2 M1 R+ _' V4 q5 Q/ M
– TFT Controller/Video Output Port
/ a3 u( C' i9 k7 C7 ^) s: R) ]— Video Input Port
! H k% G: P/ K9 @ K/ Q2 Q3 z5 y— GeodeLink PCI Bridge
2 N6 g7 v( B# v/ P: b— Security Block
& j" {5 r" u/ J' ?, ?# L■ 0.13 micron process4 z4 A0 u9 f% e. C7 C r D+ d( Q# f
■ Packaging:
. I$ H3 z# e2 \4 h' J— 481-Terminal BGU (Ball Grid Array Cavity Up) with
: H! R( @8 n5 i! H/ Q% Uinternal heatspreader
& t0 F; a% P3 W& S$ _- Y■ Single packaging option supports all features
8 X) ~) N; E# mCPU Processor Features
! V' u7 }% M5 F" R& r■ x86/x87-compatible CPU core% z: S$ p" p3 j
■ Performance:( P3 M6 F' Q* q. M& ^
— Processor frequency: up to 500 MHz
4 m8 T0 f0 D, g. @— Dhrystone 2.1 MIPs: 150 to 450
- p# O3 d7 l7 V$ }— Fully pipelined FPU
/ b0 m( V6 D8 F' V a4 F■ Split I/D cache/TLB (Translation Look-aside Buffer):
# J! J0 K- i, j% f9 n— 64 KB I-cache/64 KB D-cache
$ G, \1 p; I% ^8 J# u& J— 128 KB L2 cache configurable as I-cache, D-cache," }3 w! D# K+ g
or both, p9 N' t( M* a
■ Efficient prefetch and branch prediction* h+ S2 o: o5 A6 ^9 T
■ Integrated FPU that supports the MMX® and
$ x; B7 H- ?, M+ y" Q. T2 iAMD 3DNow!™ instruction sets
# h/ i9 I$ t3 \6 \, l" x■ Fully pipelined single precision FPU hardware with
1 L! F s2 D: }microcode support for higher precisions
" X0 t1 V: x. v+ [/ W- VGeodeLink™ Control Processor9 V3 e# |; F, p. G, j5 U: k/ D8 G
■ JTAG interface:& k( Y' Y4 U4 S/ @6 i$ \
— ATPG, Full Scan, BIST on all arrays
. r4 E1 I9 I" }— 1149.1 Boundary Scan compliant3 c% i: y8 U# e/ I
■ ICE (in-circuit emulator) interface
' O( W6 s4 M4 y4 H6 E( L. j■ Reset and clock control
3 A* j. Z8 e& }■ Designed for improved software debug methods and; @9 C4 [# _# L% i5 _8 {9 q
performance analysis5 _* Y% ]0 l2 U6 p- T6 a8 i
■ Power Management:
1 ]) d) x' {* {9 b" u— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
$ j' L' D3 ~ m3 E, e' r8 h500 MHz max power c& V3 g7 i. S- [" R7 {; x, K
— GeodeLink active hardware power management9 y& ~4 \$ r- O/ [
— Hardware support for standard ACPI software power
$ X( O0 w6 n* `& P' A' l# B" L' Imanagement% X' T6 r. n; e$ Y
— I/O companion SUSP/SUSPA power controls4 s: i, ?+ e9 T: G
— Lower power I/O' h _& O% E8 _. V* ?+ t8 O1 l# b
— Wakeup on SMI/INTR
8 D" \3 q1 O9 A# U( ?9 ^, Y$ |9 B■ Designed to work in conjunction with the
( W" s) a1 l* RAMD Geode™ CS5536 companion device6 J$ ~6 Y: Z; l, T* O2 b
GeodeLink™ Architecture
3 u* x5 `5 f* W$ E0 O/ K3 r■ High bandwidth packetized uni-directional bus for M A; z% z* b5 R$ Y. z: @
internal peripherals
) l2 q6 @ j9 c6 P■ Standardized protocol to allow variants of products to be B' d' x0 E M! F
developed by adding or removing modules
2 t( ]& o/ v, y2 B! C* p■ GeodeLink Control Processor (GLCP) for diagnostics
3 a" j A8 ?- u! x! dand scan control
" ?# D6 {: Q" Q* Y5 _■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
; _1 L- W; T/ z% K# y! D; DGeodeLink™ Memory Controller& m( s p' H) R2 G
■ Integrated memory controller for low latency to CPU and$ X. \- z) y+ m9 M6 q
on-chip peripherals
0 ?$ l3 c+ y! Z; }: |1 n* _7 W+ I; z■ 64-bit wide DDR SDRAM bus operating frequency:
* \. I6 u( D1 E' i. N2 Y) [0 w— 200 MHz, 400 MT/S" x$ ^. \& a. i
■ Supports unbuffered DDR DIMMS using up to 1 GB
8 I2 X* G& n2 |* T3 aDRAM technology7 w4 v; ?7 D2 E. i
■ Supports up to 2 DIMMS (16 devices max)0 ]& C* t I8 i. Y$ u. K. q9 }, T
2D Graphics Processor
% j" |* _/ N% h* ^8 N■ High performance 2D graphics controller( t3 e& B) z+ `" b- l1 ^
■ Alpha BLT( f2 y% G% C2 m3 g: c
■ Microsoft® Windows® GDI GUI acceleration:
1 v+ P$ v4 E2 H$ j! ]— Hardware support for all Microsoft RDP codes& ~1 h* |+ |: j& x$ o3 P& F. W
■ Command buffer interface for asynchronous BLTs
7 Z4 T. S( x o! w; Y■ Second pattern channel support( K9 R a" k5 T5 {
■ Hardware screen rotation |
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