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AMD Geode LX 800@0.9W處理器
General Features+ g% B( D$ p7 d4 d# w( B
■ Functional blocks include:
3 C; r9 D( G9 {: Y0 Q( H: N- O— CPU Core
/ y9 y; F( C/ o0 g7 m7 s— GeodeLink™ Control Processor" {5 f8 Z$ ?. _3 _7 l! @
— GeodeLink Interface Units
- p4 ~0 f# \6 Z! c4 u" o! |— GeodeLink Memory Controller# v+ f6 R% v! @* l
— Graphics Processor ^- i p# r3 y/ O8 j+ z% B
— Display Controller- w* Y% ?7 J8 u( S6 C$ T. ?
— Video Processor. h$ \* Q6 W& L6 b+ X" |% D8 z3 `
– TFT Controller/Video Output Port
: z, u' t0 `. @+ ~. s5 `+ m0 i— Video Input Port4 w& [- r% I$ J( A: M1 d
— GeodeLink PCI Bridge1 `$ I' ~2 {2 |, d
— Security Block
, @: S6 h1 Q+ c( F0 D1 M8 b■ 0.13 micron process
. o5 a5 B- I; c9 `1 U■ Packaging:0 ~/ n0 n ?2 m& l6 F3 s
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
[+ q1 s1 k q+ f8 I8 P! T( Dinternal heatspreader3 d1 E5 i, l! s$ {9 _: R
■ Single packaging option supports all features% i* q/ Q( k3 T
CPU Processor Features
% f" n* y* s% N) x% P( p! Y■ x86/x87-compatible CPU core, ~( d0 g- J2 P" c
■ Performance:! l: p3 w2 R: Q& f% A$ d
— Processor frequency: up to 500 MHz
7 w4 S5 B! Y, ?* z— Dhrystone 2.1 MIPs: 150 to 450
- ~$ @! Y& `9 C# a' \/ }" v8 x: l— Fully pipelined FPU
& X% B. u9 |" r$ I9 q: e1 G■ Split I/D cache/TLB (Translation Look-aside Buffer):& X! _. D/ X( X7 L
— 64 KB I-cache/64 KB D-cache
4 p8 `+ r/ h9 [7 W9 n0 z+ |# {2 B— 128 KB L2 cache configurable as I-cache, D-cache,
5 G- S, n2 ?5 e6 `% @or both
/ V5 I- j) i4 q8 D% f■ Efficient prefetch and branch prediction
* @" N7 z6 l2 H0 K8 {■ Integrated FPU that supports the MMX® and% e1 A7 `6 |! x
AMD 3DNow!™ instruction sets9 @: _- E: M0 S% u- G
■ Fully pipelined single precision FPU hardware with
8 l {/ H. h5 a* Y, d. u" m. k/ T' zmicrocode support for higher precisions3 N" X1 d1 Z1 D' C
GeodeLink™ Control Processor/ t! c) J) V d- j8 _6 V
■ JTAG interface:& w1 l; L9 O6 A' ^- o; `9 s0 L" {) o0 h n
— ATPG, Full Scan, BIST on all arrays
" H" \% J# T, J3 e# U/ C9 J0 S— 1149.1 Boundary Scan compliant, t9 w2 b; j' a3 n# ]
■ ICE (in-circuit emulator) interface: S8 g. X+ _4 y1 U2 T0 ?, H
■ Reset and clock control
8 z& j$ {* n; `) X3 T■ Designed for improved software debug methods and* |6 G) z _: D5 N) B4 i2 A
performance analysis- Y) c- m$ \" ?; o; d9 H% g
■ Power Management:5 U4 a' Z# \0 n; o. X1 q
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @& r6 q6 R, q; j3 H
500 MHz max power8 {( ]0 Q! u, |2 w. ?
— GeodeLink active hardware power management
$ D/ V+ h6 W( Y$ ~+ z' X— Hardware support for standard ACPI software power# u: D+ w0 }3 p
management" o K* y$ v+ i8 U9 g
— I/O companion SUSP/SUSPA power controls0 [1 X6 U: k& z! \' X
— Lower power I/O
1 x Y9 h" w, {8 J% k— Wakeup on SMI/INTR
8 e' S m5 M# Y" L■ Designed to work in conjunction with the5 y( s& o( U' r8 s( E5 K
AMD Geode™ CS5536 companion device
0 p* ?! b" u4 M* kGeodeLink™ Architecture
% q, y8 N% d' o■ High bandwidth packetized uni-directional bus for
$ c4 z4 }( H6 yinternal peripherals$ R6 Q4 s0 T9 R( g& B
■ Standardized protocol to allow variants of products to be# u8 S& t- q" l' `
developed by adding or removing modules
$ {* t. F6 U7 i; T■ GeodeLink Control Processor (GLCP) for diagnostics) {- R" n! R g. W. Y* c' e* O" F
and scan control( z0 J$ u: {0 O+ |$ w1 G& P+ N9 j
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect
' c) M- x. P) R! i( MGeodeLink™ Memory Controller
" T9 T- A3 W+ b8 G. w1 e: O■ Integrated memory controller for low latency to CPU and
. P3 @: k. u6 n- n4 ?7 ron-chip peripherals
' a6 E& O) z3 \! j) e: r' K■ 64-bit wide DDR SDRAM bus operating frequency:2 s5 |4 ?9 t% j& L) D/ w, e: ?
— 200 MHz, 400 MT/S2 ~/ Y- u" ^' b$ B) k
■ Supports unbuffered DDR DIMMS using up to 1 GB
; g2 W: F% F8 B: ZDRAM technology# f$ h( q. r. z5 n& e
■ Supports up to 2 DIMMS (16 devices max)1 N& {% l7 R! w* P
2D Graphics Processor4 p; c- d# F* t5 i
■ High performance 2D graphics controller; P6 m0 L$ i) J! ]) i/ p$ B2 Z4 E7 F
■ Alpha BLT
. s! u, S% ~5 k" {9 C■ Microsoft® Windows® GDI GUI acceleration:
$ r7 `% [9 g' V) \) E! }— Hardware support for all Microsoft RDP codes
$ y- _, `9 o/ |% o% z$ r+ ]& i■ Command buffer interface for asynchronous BLTs
' I; @; s( i8 h' B& N1 E* B k■ Second pattern channel support
2 z s# D. f8 }! P! _" h■ Hardware screen rotation |
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