Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

cnasic

Contents
0 Y4 i: \, d5 w. b& }# [List of Tables
7 {$ F. x$ o+ T1 _6 b- A) U$ CList of Figures
Symbols and Abbreviations
Physical
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
( L, L. r  O# Z; C1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
2 ADCs in Nanometer CMOS Technologies 3
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4
8 L9 j; o) @( S5 K8 F2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 5
2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6
2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 6
2 v/ n5 z7 u* y/ e9 c, Z) G9 R8 P2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9
2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10
2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11
, s( s. O: U7 e, _6 q8 d2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13
, J: b6 O" S* Y1 @4 K$ P2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 U2 b' n# T1 t$ |0 mvii
2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
' K$ m/ x/ a' t2 `; [2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . . 17
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xiii
; B. }1 t- y# I" J" `  dxxi
: W" c9 y& F/ C9 ~2 J1 [/ \. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
CONTENTS
2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 17
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
8 o6 R; i. E0 T( K3 Principle of - ADC 19
. i* g3 ?4 p* p' r/ @3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
1 A, a+ j4 j1 a( @; a# p3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 24
" o5 q8 N7 U! q( I& F/ L3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
0 ^& q, z4 {9 P! Z% j3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33
3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
$ I8 H! J8 ?# M- P+ W3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
3.4.4 Performance Comparison of Traditional - Topologies . . 46
3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
Level Approach 47
3 |7 [4 O0 M7 C# n/ K( x% L% Q4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
* n6 w4 [) x0 s; e4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
+ _/ i. |! ?; L  x3 ?4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54
4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55
4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66
4 J2 k5 E) d" H3 L+ o0 `5 m4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
- W  U1 W* o$ p- N- f; Q" K4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
4 E/ q2 [8 y% s; q4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
* g7 |8 @7 G! h: V6 |4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76
4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76
' P9 T0 Q3 I, H4 m. I3 f1 Wviii
4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82
4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87
4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
' V3 h5 K0 B: m* K4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88
5 k0 d! _  y7 q, {4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
/ J9 C7 I1 _1 q. s) G4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System
CONTENTS ix
CONTENTS
3 O- B) I/ n4 M7 O, b6 Conclusions 149
, r2 ^: f* b1 `9 w! f1 @Bibliography 151
Index 157

scan7510

看不太懂
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! O# f9 S4 G3 X8 M7 C謝大大分享

deltachen

謝謝大大的分享~知識因分享而壯大！

jjam

感覺是非常實用的內容
$ X: r/ m& B8 F9 K' P( Q/ d感謝大大的分享~~
  ~+ k# ~- V; y/ y1 V: @9 H8 c1 u希望能對SDM有所認識與了解