Low-Power Low-Voltage Sigma-Delta Modulators in Nanometer CMOS

cnasic

Contents
% e( w8 N) D& k- R# WList of Tables
" z% k6 K$ X( c9 O, ]List of Figures
Symbols and Abbreviations
Physical
1 Introduction 1
1.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
1.2 Outline of the Work . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
0 G  L, h$ \: t% ?2 j5 X2 ADCs in Nanometer CMOS Technologies 3
9 s4 n! a- Z+ I8 K8 W- d2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
2.2 Scaling-Down of CMOS Technologies . . . . . . . . . . . . . . . . . 3
2.2.1 Driving Force of the CMOS Scaling-Down . . . . . . . . . . 4
5 s4 Q4 B3 I3 K) H) D: z2.2.2 Moving into Nanometer CMOS Technologies . . . . . . . . . 5
4 t5 k# |. v1 j2.3 Impact of Moving into Nanometer CMOS to Analog Circuits . . . . . 6
2.3.1 Decreased Supply Voltage . . . . . . . . . . . . . . . . . . . 6
2.3.2 Impact on Transistor Intrinsic Gain . . . . . . . . . . . . . . 7
2.3.3 Impact on Device Matching . . . . . . . . . . . . . . . . . . 9
2.3.4 Impact on Device Noise . . . . . . . . . . . . . . . . . . . . 10
2.4 ADCs in Nanometer CMOS . . . . . . . . . . . . . . . . . . . . . . 11
2 {" W9 G: r! q# z& w1 T2.4.1 Decreased Signal Swing . . . . . . . . . . . . . . . . . . . . 13
2.4.2 Degraded Transistor Characteristics . . . . . . . . . . . . . . 13
3 `  ^+ v8 u( A" P' u) X2.4.3 Distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
( |, n& ?" [( \vii
- X9 E. p% J& t0 |3 t: |9 s2.4.4 Switch Driving . . . . . . . . . . . . . . . . . . . . . . . . . 14
2.4.5 Improved Device Matching . . . . . . . . . . . . . . . . . . . 17
7 H7 B. m, x0 E3 Lxi
xiii
- p( O! D% o9 H* S& h9 W) h* b$ S) @0 cxxi
( j6 N9 A$ N9 g% v1 A; k. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
! D' d1 j4 x# [$ g5 ?) [, P" a5 ZDefinitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xxi
; \2 u; s4 `+ w. }4 {CONTENTS
6 w1 Z  ]/ {# l4 M8 @# n( o8 K5 R2 j2.4.6 Digital Circuits Advantages . . . . . . . . . . . . . . . . . . 17
) g1 m3 E. Z0 W1 ^2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3 Principle of - ADC 19
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.2 Basic Analog to Digital Conversion . . . . . . . . . . . . . . . . . . 19
3.3 Oversampling and Noise Shaping . . . . . . . . . . . . . . . . . . . 24
& n, o! D+ u" e! _& T3.3.1 Oversampling . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.3.2 Noise Shaping . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.3.3 - Modulator . . . . . . . . . . . . . . . . . . . . . . . . 29
3 \- u$ h# X, b: n6 V1 d6 ^) r3.3.4 Performance Metrics for the - ADC . . . . . . . . . . . . 31
3.4 Traditional - ADC Topology . . . . . . . . . . . . . . . . . . . . 33
" R. `: p) v" N0 i3.4.1 Single-Loop Single-Bit - Modulators . . . . . . . . . . . 33
; V9 l) W0 t: c$ U; L% N2 _3.4.2 Single-Loop Multibit - Modulators . . . . . . . . . . . . 37
3.4.3 Cascaded - Modulators . . . . . . . . . . . . . . . . . . 39
: H2 j/ Z! W6 x6 F3.4.4 Performance Comparison of Traditional - Topologies . . 46
: t; J' Q( w& W$ h9 m3.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
; x3 b6 ^' e; f$ y/ ?# ^4 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: Circuit
Level Approach 47
; d9 M% X- J; i: {4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47
8 Y/ v! {# t6 Y0 j4 S$ a6 G4.2 Low-Voltage Low-Power OTA Design . . . . . . . . . . . . . . . . . 48
4.2.1 Gain Enhanced Current Mirror OTA Design . . . . . . . . . . 49
7 y/ U/ f/ ~, @9 i) q7 l# y4.2.2 A Test Gain-Enhanced Current Mirror OTA . . . . . . . . . . 53
4.2.3 Implementation and Measurement Results . . . . . . . . . . . 54
3 {6 p$ T, g2 v* M# A4.2.4 Two-Stage OTA Design . . . . . . . . . . . . . . . . . . . . 55
4.3 Low-Voltage Low-Power - ADC Design . . . . . . . . . . . . . . 66
$ F+ A7 O# @2 _. `% U4.3.1 Impact of Circuit Nonidealities to - ADC Performance . . 66
4.3.2 Modulator Topology Selection . . . . . . . . . . . . . . . . . 67
& K! [% ~! k# H$ @( T" Z4.3.3 OTA Topology Selection . . . . . . . . . . . . . . . . . . . . 69
4.3.4 Transistor Biasing . . . . . . . . . . . . . . . . . . . . . . . 75
+ I* J: d" p; u  p% V4.3.5 Scaling of Integrators . . . . . . . . . . . . . . . . . . . . . . 75
0 K- J8 E/ a$ F  l% K) I  t! T4.4 A 1-V 140-μW- Modulator in 90-nm CMOS . . . . . . . . . . . 76
! `7 T* g. `7 E9 b% t6 B; ~: K! \4.4.1 Building Block Circuits Design . . . . . . . . . . . . . . . . 76
viii
4.4.2 Implementation . . . . . . . . . . . . . . . . . . . . . . . . . 80
$ n0 g* J8 c& |: ?4.4.3 Measurement Results . . . . . . . . . . . . . . . . . . . . . . 82
$ s8 j& W5 X+ t% g. \$ n1 g' i  u4.5 Measurements on PSRR and Low-Frequency Noise Floor . . . . . . . 87
9 h% p5 s+ G9 N$ a8 t' P4.5.1 Introduction of PSRR . . . . . . . . . . . . . . . . . . . . . . 87
4.5.2 PSRR Measurement Setup . . . . . . . . . . . . . . . . . . . 88
$ {  o. ^7 L' V# w1 |* Z2 x4.5.3 PSRR Measurement Results . . . . . . . . . . . . . . . . . . 88
4.5.4 Measurement on Low-Frequency Noise Floor . . . . . . . . . 95
+ G" v1 J" e: c* L# G3 p4.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
! F+ B- ]+ D) ~  i! M; V" W5 Low-Power Low-Voltage - ADC Design in Nanometer CMOS: System
CONTENTS ix
; S! `1 t" p9 t) @, Y8 uCONTENTS
6 Conclusions 149
! D  C! u  w: O; ^Bibliography 151
4 r/ `# u5 ~. x  U) i& [1 zIndex 157

scan7510

看不太懂
可能還沒學過吧
現在只能單純推一下
謝大大分享

deltachen

謝謝大大的分享~知識因分享而壯大！

jjam

感覺是非常實用的內容
) [, y& o  [1 s4 Y, {9 R感謝大大的分享~~
希望能對SDM有所認識與了解