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AMD Geode LX 800@0.9W處理器
General Features) O5 Q, v2 f8 ~+ ^) l( z) Q. f
■ Functional blocks include:9 L% }, @) o1 E% Q3 C# D
— CPU Core) j7 \4 R6 {$ W; J! L( l
— GeodeLink™ Control Processor6 l% J+ K9 _! Q
— GeodeLink Interface Units
) Q1 M1 Z. J @; Y— GeodeLink Memory Controller( f6 i) ~+ B: ^+ f, r+ V- G `1 k
— Graphics Processor
9 z% L9 s/ E9 A' M— Display Controller
4 v! F' R; Y/ |5 m: i— Video Processor& N0 k m7 B- S o
– TFT Controller/Video Output Port
k% }' U& D4 r- X+ j— Video Input Port
; J6 X& y; O5 U" O) z3 U2 @— GeodeLink PCI Bridge8 \6 O( ?9 X) s4 q7 K7 v O; O
— Security Block
0 I7 R- W- z g- L3 N. C■ 0.13 micron process4 H% u1 C% l8 z% p- U, `; _4 n
■ Packaging:
( K& E5 \" u9 h+ i1 U/ O— 481-Terminal BGU (Ball Grid Array Cavity Up) with
" }' s) e2 U% v! [3 h9 linternal heatspreader8 s& U# h3 d7 D" q2 U" K
■ Single packaging option supports all features
, @3 e2 Q# l# y( z! n# VCPU Processor Features
, D- P2 z! ]( \& z■ x86/x87-compatible CPU core
6 P' e4 `# A8 Y8 d■ Performance:* K! P# r% } F0 K+ W9 [
— Processor frequency: up to 500 MHz
7 E5 X/ }: y" ]— Dhrystone 2.1 MIPs: 150 to 450
- ]# O2 Y A9 t- ] \+ r+ x— Fully pipelined FPU
0 M8 y7 s' o" B* m+ R■ Split I/D cache/TLB (Translation Look-aside Buffer):
! R4 S7 D7 o% V— 64 KB I-cache/64 KB D-cache
- [- A# }5 V% s2 u2 o5 s# g3 L" B- I— 128 KB L2 cache configurable as I-cache, D-cache,
1 y% C( M2 ], d5 Q. ^! m3 t lor both. J' j- u X! @& b3 M
■ Efficient prefetch and branch prediction4 o1 r- A# |3 \4 C* E A
■ Integrated FPU that supports the MMX® and
# ?$ ]+ H0 p8 y" J- X) dAMD 3DNow!™ instruction sets7 ], w7 a, r% x0 d9 s6 K' {
■ Fully pipelined single precision FPU hardware with
8 Y$ B! H0 E* I. Ymicrocode support for higher precisions+ n/ C/ e2 u" L) f- t; k, Q
GeodeLink™ Control Processor
% I. I: W- v$ t4 V; e■ JTAG interface:! n$ Y6 w5 f0 V! ^
— ATPG, Full Scan, BIST on all arrays
o+ o3 ]( o3 c9 \2 H6 l— 1149.1 Boundary Scan compliant
1 u4 M# x1 l, h. B A■ ICE (in-circuit emulator) interface
8 c2 Q) S: }' t8 l, l■ Reset and clock control- g, O7 V& W: ^- D* ~; q
■ Designed for improved software debug methods and
- `" z i! ^$ I, m# Gperformance analysis
# A% m4 z$ `6 M2 I; f7 w■ Power Management:7 i c" j- C0 q7 [; u, ?
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @# Y9 e6 r; u! T2 i
500 MHz max power; I; ~1 e& X8 G( e) o f) G# J
— GeodeLink active hardware power management( m( n* B% }; t' R( X
— Hardware support for standard ACPI software power* F5 l- R; @/ y. ?) W
management: E, e7 }; K" W! o
— I/O companion SUSP/SUSPA power controls) {, Y" V3 n! l
— Lower power I/O
& O/ p) n5 v2 J O. a7 M— Wakeup on SMI/INTR
: A6 u- D9 @' V+ G" E■ Designed to work in conjunction with the
2 R$ ~8 j9 b6 P' |2 y/ s6 [AMD Geode™ CS5536 companion device
) ~( o- z% J2 i w8 ]; LGeodeLink™ Architecture
8 s1 A$ \+ v/ E! f■ High bandwidth packetized uni-directional bus for
& N& l# g4 v. N$ \$ p+ Ginternal peripherals
7 M+ i, K `8 x/ E■ Standardized protocol to allow variants of products to be: Y% D8 ]0 {2 Z* J0 m5 D! e
developed by adding or removing modules
P( g( |, J$ N/ n$ a# j" Q■ GeodeLink Control Processor (GLCP) for diagnostics
, \/ i) G+ r8 P' e; l" mand scan control- h* g# `( T& o% A, k5 _
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect% a3 e+ W! g l7 Q8 T8 B
GeodeLink™ Memory Controller' O6 Z5 N1 {( s4 }
■ Integrated memory controller for low latency to CPU and
, L5 F: I/ X* W3 ?& `on-chip peripherals
, I* Q I3 }1 P" G% n. I, N4 E■ 64-bit wide DDR SDRAM bus operating frequency:
$ J3 D7 v; ^% W* x2 R— 200 MHz, 400 MT/S: Z/ \# ?4 q6 g: y4 O
■ Supports unbuffered DDR DIMMS using up to 1 GB
" c4 D8 F, { i# u+ }DRAM technology
. w5 ?# J' d/ z. l■ Supports up to 2 DIMMS (16 devices max)
! N; b+ U. L2 S6 T. @% E2D Graphics Processor+ ?' O: r7 V, Y2 K0 K& D% ?
■ High performance 2D graphics controller
/ d- c5 G' ]- \& k7 ] R■ Alpha BLT
5 m8 _1 b6 }' l* W) o ]) ^■ Microsoft® Windows® GDI GUI acceleration:
8 |- K& v7 x7 h' e& F0 w, M— Hardware support for all Microsoft RDP codes7 T- y+ u% U4 L8 E5 p
■ Command buffer interface for asynchronous BLTs
' e6 u7 X1 V9 q8 c■ Second pattern channel support; F! n7 ~3 A4 [7 i
■ Hardware screen rotation |
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