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AMD Geode LX 800@0.9W處理器
General Features& m- E. }: v; r! f: X' i: P2 N9 o& Y; z# b
■ Functional blocks include:/ s& F+ E, b& f) ?
— CPU Core
# v$ ?& n! u5 D$ w— GeodeLink™ Control Processor) ~( G$ W; m5 j' \
— GeodeLink Interface Units
, X; @! {: k4 B; o/ S) \— GeodeLink Memory Controller
3 c5 g- ]; J* @3 I; L( p— Graphics Processor
v1 B1 Q1 G1 R3 U! U0 K— Display Controller( j5 C" q( J% G7 X9 S5 S
— Video Processor
# ^) C1 C: T R! O" u– TFT Controller/Video Output Port
" l7 H6 ^0 Y& q— Video Input Port
7 O7 D8 ]2 ]4 N6 s Z— GeodeLink PCI Bridge
4 Y' r# I( r5 x3 j— Security Block
) C# P0 e+ ?7 T% k& e■ 0.13 micron process t. C' W$ B* i2 K
■ Packaging:
# h' J9 X$ h$ R: e1 Y7 B" {— 481-Terminal BGU (Ball Grid Array Cavity Up) with9 G2 ~$ Y$ v9 Z* l8 l$ t
internal heatspreader
8 U( O2 x9 o2 D$ ?; t- J! ]: `■ Single packaging option supports all features- n$ O7 R h/ \4 P- G! `5 t
CPU Processor Features
* x, Q3 \: E4 q f: J+ g; s" A8 \■ x86/x87-compatible CPU core
" m# r+ z0 ]( z' l1 q; }■ Performance:; f- t6 H2 D5 @; u- `
— Processor frequency: up to 500 MHz
/ \) i: n5 A3 W8 K, Q— Dhrystone 2.1 MIPs: 150 to 4501 m+ U" q( O2 P% i; b
— Fully pipelined FPU
7 z2 S3 d0 }1 @3 N■ Split I/D cache/TLB (Translation Look-aside Buffer):5 g$ J; e4 D! j' d' N3 r
— 64 KB I-cache/64 KB D-cache
8 F, T0 a8 S9 t: I" `+ u8 p— 128 KB L2 cache configurable as I-cache, D-cache,$ ~4 Q8 i+ W* r( A" q) m
or both
# z5 E+ x4 q0 x/ k+ z■ Efficient prefetch and branch prediction! B2 v# Y3 I( I6 b
■ Integrated FPU that supports the MMX® and
# A: _% U- l H5 Z. i& M9 IAMD 3DNow!™ instruction sets
& M; w n+ O3 p( T" [( O8 Z! T■ Fully pipelined single precision FPU hardware with
( W% R h% u" e* P* Y0 Amicrocode support for higher precisions$ y+ J7 O, U) K- r' u' g4 `
GeodeLink™ Control Processor" r) \1 _# u% }/ r
■ JTAG interface:
' r6 s& |- h" K' A8 n" b— ATPG, Full Scan, BIST on all arrays
+ a& A3 C" @% U0 s2 V" d8 @— 1149.1 Boundary Scan compliant; Y% T" d. ~$ s8 j
■ ICE (in-circuit emulator) interface
: _5 E3 l/ s7 c& }% S6 a1 [■ Reset and clock control+ \+ k2 X9 q4 h/ A/ i
■ Designed for improved software debug methods and
6 {. K0 ?/ V& D K7 @8 W6 ], \/ Tperformance analysis
3 x$ c2 k: e3 j; J% j- |6 L■ Power Management:
, ~ q, [) [9 N$ X— Total Dissipated Power (TDP) 3.8W, 1.6W typical @
( G* I1 ^+ l7 W2 z/ |500 MHz max power a! @$ W( C F- C: Y4 q5 s0 R# s
— GeodeLink active hardware power management1 c; i5 C2 \/ d: ?) p8 o
— Hardware support for standard ACPI software power# S& D; [% I5 c, F2 a+ e7 k" R
management
) @; Z- N* D1 r8 p4 d# D3 T— I/O companion SUSP/SUSPA power controls
# S1 D% S0 e, N- \) X- M6 z0 U— Lower power I/O0 k$ s( N- z, \) n
— Wakeup on SMI/INTR
" ^8 Z, _: P9 z2 z8 ?* s■ Designed to work in conjunction with the
/ h$ m5 t; y0 ]& m$ GAMD Geode™ CS5536 companion device
# l4 s/ l- y, ?6 h% r1 I; M/ RGeodeLink™ Architecture
) |- v2 K* W3 L" Z2 w. |" T■ High bandwidth packetized uni-directional bus for
/ I7 |, \$ s$ b$ ~: ?4 t" J5 kinternal peripherals* n* A4 s+ | \; y: L
■ Standardized protocol to allow variants of products to be5 r) ?" g4 L4 ~6 |7 T) c7 U
developed by adding or removing modules1 F- l5 Y7 U, ` i1 G' M$ d
■ GeodeLink Control Processor (GLCP) for diagnostics9 l, Y1 `) f5 }" G4 _( a% k* _+ G
and scan control) ^% {. j1 K! `2 L! j/ j) w
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect* W# |" F/ z! u8 B5 N! _
GeodeLink™ Memory Controller
$ L4 Q s; b- ^+ x2 u% w0 s■ Integrated memory controller for low latency to CPU and* S5 g# A' j. \% Y
on-chip peripherals
4 j) }" U2 B, p6 {& J1 |■ 64-bit wide DDR SDRAM bus operating frequency:
( q" P: {! X1 ]0 L— 200 MHz, 400 MT/S
9 y1 l$ O6 k9 R' x( b■ Supports unbuffered DDR DIMMS using up to 1 GB
: D8 D; V$ Z" ]7 P' PDRAM technology5 D* }, T& r. |, P, w. }
■ Supports up to 2 DIMMS (16 devices max)8 S1 Z+ @4 s# p3 K+ M: x5 q) }+ Z
2D Graphics Processor
6 r; k" b: e5 W! G1 I9 f■ High performance 2D graphics controller
* [& u F& _6 k, l A, ]( p■ Alpha BLT
/ |7 R2 }7 X. R5 V- a■ Microsoft® Windows® GDI GUI acceleration:
2 [% {) W& J8 o2 `$ n— Hardware support for all Microsoft RDP codes
2 e4 {" |; B# E■ Command buffer interface for asynchronous BLTs
6 y2 n) E- S% x7 d4 q* E■ Second pattern channel support
6 O, z1 H) N+ ~1 m% G, ?& B) R■ Hardware screen rotation |
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