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AMD Geode LX 800@0.9W處理器
General Features2 n( E4 T/ ?7 `+ e
■ Functional blocks include:$ m# l6 ^0 T8 s8 R* X+ V9 f
— CPU Core
' H; R: ^* b+ c) a. e) C— GeodeLink™ Control Processor) ?% u) P6 J' z, I
— GeodeLink Interface Units
; L6 ?8 r9 n5 p/ u8 }— GeodeLink Memory Controller5 T% b" f. _3 O' x5 l, G3 a, J; C
— Graphics Processor
8 b, h" I7 ]! k9 O— Display Controller& @7 q6 u/ T3 ?# z/ o
— Video Processor
% V0 N$ Z& w/ @+ g$ ], n" @+ N– TFT Controller/Video Output Port" A$ @: @% c% o
— Video Input Port: G/ L/ {' \* C. u; o G
— GeodeLink PCI Bridge+ k. J9 {& Z$ Z) J( H
— Security Block
4 u _1 {' b1 j) ^, i4 P/ w5 y! @■ 0.13 micron process! j0 D& z1 [: \' Y
■ Packaging:, P: O" C' H6 Z3 `8 C/ m# A* H
— 481-Terminal BGU (Ball Grid Array Cavity Up) with
( b' F, Q7 h: Y4 W! O- q1 b/ T2 `internal heatspreader
8 t, ~3 H) @) ^8 g5 o' t6 F■ Single packaging option supports all features6 ^/ l2 u, s+ @/ M' c! K
CPU Processor Features$ H, p& h$ ]5 z) O6 ?
■ x86/x87-compatible CPU core% t1 C8 \9 |% m! `$ \ _# I
■ Performance:2 `* L* s# I, u
— Processor frequency: up to 500 MHz
4 W y: P( e- p) @ j— Dhrystone 2.1 MIPs: 150 to 450
7 g, g7 Y6 ?5 o, z$ i7 V; Z— Fully pipelined FPU
; d. Z2 L; b* X7 z$ Z■ Split I/D cache/TLB (Translation Look-aside Buffer):0 j( u" J9 K2 O0 {
— 64 KB I-cache/64 KB D-cache
1 Y/ x, M/ f v, U/ X% a— 128 KB L2 cache configurable as I-cache, D-cache,+ p* ]- U8 G$ |2 Z, n
or both- G) B3 a7 L. R' M% M. E! V& H
■ Efficient prefetch and branch prediction
# H& k \) U2 M& s* j S$ J6 j■ Integrated FPU that supports the MMX® and
! x& P1 o/ l- G4 C7 g# d/ E8 M+ gAMD 3DNow!™ instruction sets) l' \+ m6 `6 u w# w& {
■ Fully pipelined single precision FPU hardware with
1 `% V/ [ ~7 s$ imicrocode support for higher precisions
4 v5 U. b- A4 b5 l5 L% y& uGeodeLink™ Control Processor
( i, e8 `" V7 b8 q) Y■ JTAG interface:* _- R( Q9 f1 a) F
— ATPG, Full Scan, BIST on all arrays" P# h9 G7 O8 z( ~6 s
— 1149.1 Boundary Scan compliant) a5 t7 r* @! b! b% P+ u$ L
■ ICE (in-circuit emulator) interface
; `. [& d8 M- Q2 ?: I" a3 |: k■ Reset and clock control8 r" D4 H0 g7 E6 w2 r( F" i( Q9 c
■ Designed for improved software debug methods and
6 m6 c5 k+ m% y& x* Qperformance analysis1 R8 H" P5 {4 B( P7 j7 o
■ Power Management:
, q; U2 A% E6 v1 G; q— Total Dissipated Power (TDP) 3.8W, 1.6W typical @; }( ~" [# U8 v
500 MHz max power$ M" s/ C1 x# G: i% ^4 U
— GeodeLink active hardware power management
7 m" I% J1 L. C8 k— Hardware support for standard ACPI software power
- Y( x; ]5 P+ e0 R, `& ?management1 W! C) D4 X Y0 F7 I) U
— I/O companion SUSP/SUSPA power controls
/ S& v3 z% U, c5 c* _- R5 E— Lower power I/O- n3 _, i: l8 ?! K# }' l- y
— Wakeup on SMI/INTR. e8 C+ g6 P8 \! ~( {
■ Designed to work in conjunction with the; L- ^- Z4 c4 S3 R* P. D$ `
AMD Geode™ CS5536 companion device
+ ~+ ~9 w) T" G: \1 G( IGeodeLink™ Architecture
" |; F2 n2 U, A7 w2 u# `- _/ B■ High bandwidth packetized uni-directional bus for5 T4 k: w6 z9 n" v! e2 A/ b
internal peripherals' j. S& p& c$ i: |2 M5 F
■ Standardized protocol to allow variants of products to be0 \( N; g/ U8 X$ K3 v5 { T
developed by adding or removing modules! G% k2 p$ y C' ~. A
■ GeodeLink Control Processor (GLCP) for diagnostics3 {2 g/ K/ B* g7 p- d3 T9 K# Y1 P
and scan control
6 \: n d$ b& b* O! _7 y! f■ Dual GeodeLink Interface Units (GLIUs) for device interconnect/ K$ a; y' O$ y, c8 W
GeodeLink™ Memory Controller$ J$ {9 Z1 _# d$ e8 Y
■ Integrated memory controller for low latency to CPU and' C, E* l" C' F+ ~
on-chip peripherals$ Y* K6 i2 u/ X8 {1 @
■ 64-bit wide DDR SDRAM bus operating frequency:1 c2 r+ B* |; A
— 200 MHz, 400 MT/S. L' d# G, ?8 U! T' X6 C
■ Supports unbuffered DDR DIMMS using up to 1 GB2 W: l% Z7 }( f
DRAM technology
5 ~' S1 a( m9 p■ Supports up to 2 DIMMS (16 devices max)* T B% F" | n. ~2 t: b1 e
2D Graphics Processor Q' y! C/ Z( @8 Q) P% k: a
■ High performance 2D graphics controller" s9 [" L: g: z9 J
■ Alpha BLT
* w7 J, G$ i4 J( K■ Microsoft® Windows® GDI GUI acceleration:& R. k* L, `+ l" j2 a9 z* I- l u
— Hardware support for all Microsoft RDP codes8 B: I6 t" ~7 i+ l5 Q' @
■ Command buffer interface for asynchronous BLTs) x5 A' O& K7 L3 }5 k) B: \6 @- q
■ Second pattern channel support
, C- J9 O/ W: Y; F■ Hardware screen rotation |
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