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【工作內容】* B6 s" j! n* @4 \6 Y
先進製程與模組開發 (DRAM/ Flash/ Logic)" J3 G( `1 L0 D6 J8 E4 L
- Photolithography (e-beam, EUV, OPC/RET, Photo Resist Materials),9 R. L! t" C6 d! \0 Q
Dry Etch, Cleaning & CMP, Diffusion, Ion Implantation, Metallization,3 Y& }! i- _2 L, x
Metrology & Inspection, etc.
- b! h. _- t' k* \9 Z: Z# B- Device Isolation, Transistor, Capacitor, Dielectric
" N: `' a% u c4 l( b+ u/ A2 r: t- High-K/Metal Gate, SiO2/SiON Gate Dielectric6 I% S1 y, A7 {. W
- Low-K, Interconnect, etc.
0 K3 t, ~3 w( a/ K+ r& T※ OPC: Optical Proximity Correction (Comput. Litho)
/ n! q& L& _7 S: B+ _4 m! R MPC: Mask Process Correction/ Z* x0 l/ e: Q* ?6 Q8 r, Z. a! a
7 ^4 Z( e2 ?% R+ Y' C4 ]
FEOL/BEOL 製程整合 (DRAM/ Flash/ Logic)3 f# n, S. ?/ U# @6 H+ _- ]. w
新型記憶體: PRAM, STT-MRAM, ReRAM3 i0 P/ S( E- w4 C' l
TCAD/ECAD5 e n- K, P3 o' G1 M$ j
- Process & Device/Material Modeling, Circuit Compact/Reliability Modeling4 k6 R) x- M* g5 m: C" k& N X
- Circuit Simulator Development
# X) m4 o& s v( G( k; @- System-Level Modeling/Simulation, Virtual Platform, HW/SW Co-Design
7 F; j9 q5 t$ g5 w: q- Simics/CoWare/SOC Designer UserMemory Controller/Memory Architecture/ ]' C( y2 J7 _& J, B
SSD Research Experience |
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