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【工作內容】3 f1 w' v8 J# n# {
先進製程與模組開發 (DRAM/ Flash/ Logic)
* m" {/ r2 ]9 t$ \7 [7 l- Photolithography (e-beam, EUV, OPC/RET, Photo Resist Materials),' {" G+ {& i0 @- x5 M+ H
Dry Etch, Cleaning & CMP, Diffusion, Ion Implantation, Metallization,
: d6 M6 j, t: b1 [$ t3 } Metrology & Inspection, etc.
% \, D& g4 F% V; l* D |2 Z- Device Isolation, Transistor, Capacitor, Dielectric
$ x+ w( K2 z |5 l: u- High-K/Metal Gate, SiO2/SiON Gate Dielectric+ z/ z- c: }$ j6 o6 [4 m
- Low-K, Interconnect, etc.
2 ~/ `% S o5 p) S R. {, z' H& E※ OPC: Optical Proximity Correction (Comput. Litho)
7 Q; L! v5 A4 |+ F/ g MPC: Mask Process Correction+ l7 K6 b5 k1 ], Y V
) H8 m3 t. y R+ e5 ]
FEOL/BEOL 製程整合 (DRAM/ Flash/ Logic)5 S0 }- u5 H R7 i1 s' G* o
新型記憶體: PRAM, STT-MRAM, ReRAM
, n/ x/ s9 }: ?+ W/ j7 @. qTCAD/ECAD: v" Q7 e% x: u, R4 \
- Process & Device/Material Modeling, Circuit Compact/Reliability Modeling, q8 D: [8 j7 E: p3 z4 l0 I
- Circuit Simulator Development* T- n; x0 j6 Y' K5 x
- System-Level Modeling/Simulation, Virtual Platform, HW/SW Co-Design7 I3 x; C7 O; Z! G$ n* Z5 p
- Simics/CoWare/SOC Designer UserMemory Controller/Memory Architecture/
$ q: L8 ^* {7 }4 Q3 j6 | SSD Research Experience |
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