關於undersampling ADC的問題

jeffsky

設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
! t( A! o, T# B' V9 I或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

jeffsky

原帖由 jeffsky 於 2007-11-8 02:07 PM 發表
設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？/

DennyT

17MHz 的 tone 會不會是系統OSC or XTAL 的 16.667MHz clock feedthrough noise?

- u) Q" _0 n. v因為即使是under sampling, alias image in first order term: (FS=54MHz, Ft=44MHz, Nyquist band=27MHz)
FS-Ft=54-44=10MHz
FS+Ft=54+44=98MHz (folding 回 Nyquist band=10MHz)

8 _/ J# m: J+ L; Q' `: ^2nd order term:
4 T) l4 |- j; y4 d7 V% e2FS-Ft=108-44=64MHz (folding 回 Nyquist band=10MHz)
( s2 T8 }2 Y! b' d2FS+Ft=108+44=152MHz (folding 回 Nyquist band=10MHz)
|FS-2Ft|=54-88=34MHz (folding 回 Nyquist band=20MHz)
/ i( Q' w0 _9 G$ G4 K/ _) E1 ]FS+2Ft=54+88=142MHz (folding 回 Nyquist band=20MHz)
+ R$ g% a8 ~$ U/ F2 H
2nd~7th Harmonic:
6 I/ C: K, V- j* T2nd = 20MHz
. N4 X" S! C) P  ]- O2 g' I9 u3rd = 30MHz  (folding 回 Nyquist band=24MHz)
4th = 40MHz  (folding 回 Nyquist band=14MHz)
5th = 50MHz  (folding 回 Nyquist band=4MHz)
6th = 60MHz  (folding 回 Nyquist band=6MHz)
7th = 70MHz  (folding 回 Nyquist band=16MHz)
  l% u9 O: B, v) ^3 }6 G你附的Frequency domain plot 在6th之後已在noise floor之下了, 故之後的harmonic可略去不計,
但是就是沒有17MHz的theoretical noise source.
來個Maxim AN928 anti-aliasing filter的文件:
' U2 U! p9 a7 R8 Z& {: b: d
. ~! c* g8 x0 B; k" F2 m+ n( W[ 本帖最後由 DennyT 於 2007-11-10 12:00 AM 編輯 ]

jeffsky

Thank you for your kind reply.
% c1 `$ w- `& z% u4 v+ `( }3 o  hI have ever seen a paper or something else to say that when the signal frequency approaches the sample rate, the beat frequency is easy to appear at Fsig-Fs/2, for example, this frequency is 17MHz. It is as if sampling frequency is 27MHz. It is really a puzzle.

DennyT

有此一說:
! s0 }5 q' p; a5 M當Fin接近於Fs/2時, ADC sample的電壓slew at full scale, 此時奇數點之間的壓差其實很小 (偶數點亦同), 但是相鄰兩點間的壓差卻很大, 測試上又稱為ADC envelope test, 而在此測試中被引進來的 "beat frequency" 會被視為noise, 使SNR下降.

: N1 V/ y6 e% V( v8 |: @) Y也就是說, 若ADC內front end的PGA or buffer Amp slew rate不足, 此缺陷便很容易在此測試中被突顯出來.

+ k" `: ~# E( `6 Q3 a/ z就系統面而言, 拉高ADC的AVDD看看有沒有救, (ADC PAD_VDD反而要調低, 除了降EMI外也可拉低系統noise floor).
# a. g2 {9 t/ s; y  V
7 O6 L. K7 d0 U6 Y3 v/ l  q. r[ 本帖最後由 DennyT 於 2007-11-12 10:29 PM 編輯 ]

jeffsky

I am really thankful to DennyT's reply, it is a reasonable and constructive explanation on this issue. I will try to pull higher supply voltage to see if it can be relieved or removed or not. Thank you very much.