關於undersampling ADC的問題

jeffsky

設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

jeffsky

原帖由 jeffsky 於 2007-11-8 02:07 PM 發表
3 _/ A" c5 p1 u0 ]% o設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
# R" \  I9 G. M8 A0 Z7 t: K" }或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

2 b# i# a2 Y* Q$ b+ ]？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？/
3 K, M, G0 h4 f4 M) }9 L8 o

DennyT

17MHz 的 tone 會不會是系統OSC or XTAL 的 16.667MHz clock feedthrough noise?
* o* q6 @8 \2 A; m5 ~& o
因為即使是under sampling, alias image in first order term: (FS=54MHz, Ft=44MHz, Nyquist band=27MHz)
FS-Ft=54-44=10MHz
FS+Ft=54+44=98MHz (folding 回 Nyquist band=10MHz)

: z0 z8 c, x2 V4 u6 L; _1 B2nd order term:
. P+ ]' v/ l+ h) F2FS-Ft=108-44=64MHz (folding 回 Nyquist band=10MHz)
% s+ C! J" }) ]3 v2FS+Ft=108+44=152MHz (folding 回 Nyquist band=10MHz)
9 ?) t1 S9 |5 W( B|FS-2Ft|=54-88=34MHz (folding 回 Nyquist band=20MHz)
FS+2Ft=54+88=142MHz (folding 回 Nyquist band=20MHz)

2nd~7th Harmonic:
* A2 V# e; r% ?( K& K" ]0 ~$ F1 [% ?2nd = 20MHz
+ N( m6 b% f& V+ i3 _1 Z; X9 z3rd = 30MHz  (folding 回 Nyquist band=24MHz)
5 j. N% r0 o5 I( s4 D4th = 40MHz  (folding 回 Nyquist band=14MHz)
0 I( W$ r% g& ~& S4 F5th = 50MHz  (folding 回 Nyquist band=4MHz)
3 l, F$ n8 V6 s6th = 60MHz  (folding 回 Nyquist band=6MHz)
7th = 70MHz  (folding 回 Nyquist band=16MHz)
% y+ g: ^# l0 b" |5 h& a3 q你附的Frequency domain plot 在6th之後已在noise floor之下了, 故之後的harmonic可略去不計,
但是就是沒有17MHz的theoretical noise source.
' b9 a/ s: ?5 O5 Q9 @* x來個Maxim AN928 anti-aliasing filter的文件:
  e7 p1 ]: c* v9 [/ v
[ 本帖最後由 DennyT 於 2007-11-10 12:00 AM 編輯 ]

jeffsky

Thank you for your kind reply.
I have ever seen a paper or something else to say that when the signal frequency approaches the sample rate, the beat frequency is easy to appear at Fsig-Fs/2, for example, this frequency is 17MHz. It is as if sampling frequency is 27MHz. It is really a puzzle.

DennyT

有此一說:
當Fin接近於Fs/2時, ADC sample的電壓slew at full scale, 此時奇數點之間的壓差其實很小 (偶數點亦同), 但是相鄰兩點間的壓差卻很大, 測試上又稱為ADC envelope test, 而在此測試中被引進來的 "beat frequency" 會被視為noise, 使SNR下降.

$ X( z% N4 O9 u5 Z5 L; q也就是說, 若ADC內front end的PGA or buffer Amp slew rate不足, 此缺陷便很容易在此測試中被突顯出來.

: @5 u4 d7 b, _9 \) f. Z8 I) J. T就系統面而言, 拉高ADC的AVDD看看有沒有救, (ADC PAD_VDD反而要調低, 除了降EMI外也可拉低系統noise floor).
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: p% J4 O2 y& e+ k1 E3 W! ]4 Q3 u[ 本帖最後由 DennyT 於 2007-11-12 10:29 PM 編輯 ]

jeffsky

I am really thankful to DennyT's reply, it is a reasonable and constructive explanation on this issue. I will try to pull higher supply voltage to see if it can be relieved or removed or not. Thank you very much.