關於undersampling ADC的問題

jeffsky

設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

jeffsky

原帖由 jeffsky 於 2007-11-8 02:07 PM 發表
$ @: f1 c: k  O% t- F$ K設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？/

DennyT

17MHz 的 tone 會不會是系統OSC or XTAL 的 16.667MHz clock feedthrough noise?
" Y% E& M2 z$ h, m8 o; m0 {
- v( d6 ?! O" L* g因為即使是under sampling, alias image in first order term: (FS=54MHz, Ft=44MHz, Nyquist band=27MHz)
FS-Ft=54-44=10MHz
* t/ x: B) f+ h: H" f0 {% C  }4 cFS+Ft=54+44=98MHz (folding 回 Nyquist band=10MHz)

2nd order term:
2FS-Ft=108-44=64MHz (folding 回 Nyquist band=10MHz)
& L  V8 \2 C0 E2FS+Ft=108+44=152MHz (folding 回 Nyquist band=10MHz)
4 z5 [" [4 Z3 B|FS-2Ft|=54-88=34MHz (folding 回 Nyquist band=20MHz)
FS+2Ft=54+88=142MHz (folding 回 Nyquist band=20MHz)
2 ?% \& S& r! @1 r9 ]
2nd~7th Harmonic:
* F: G3 W$ \9 i9 |2nd = 20MHz
3rd = 30MHz  (folding 回 Nyquist band=24MHz)
4th = 40MHz  (folding 回 Nyquist band=14MHz)
5th = 50MHz  (folding 回 Nyquist band=4MHz)
6th = 60MHz  (folding 回 Nyquist band=6MHz)
1 ]3 S9 x/ t( r: X3 l% c2 g7th = 70MHz  (folding 回 Nyquist band=16MHz)
" _  n0 R( W) D9 @. c你附的Frequency domain plot 在6th之後已在noise floor之下了, 故之後的harmonic可略去不計,
6 c1 w/ }$ X5 H+ o但是就是沒有17MHz的theoretical noise source.
來個Maxim AN928 anti-aliasing filter的文件:
/ |) p9 A  [( S( h/ M
5 j, ^, ^9 e4 a1 @2 G7 B' `9 c[ 本帖最後由 DennyT 於 2007-11-10 12:00 AM 編輯 ]

jeffsky

Thank you for your kind reply.
I have ever seen a paper or something else to say that when the signal frequency approaches the sample rate, the beat frequency is easy to appear at Fsig-Fs/2, for example, this frequency is 17MHz. It is as if sampling frequency is 27MHz. It is really a puzzle.

DennyT

有此一說:
+ j' ~- G8 O9 }/ M* [3 }當Fin接近於Fs/2時, ADC sample的電壓slew at full scale, 此時奇數點之間的壓差其實很小 (偶數點亦同), 但是相鄰兩點間的壓差卻很大, 測試上又稱為ADC envelope test, 而在此測試中被引進來的 "beat frequency" 會被視為noise, 使SNR下降.
# S' H( g: U4 a
也就是說, 若ADC內front end的PGA or buffer Amp slew rate不足, 此缺陷便很容易在此測試中被突顯出來.
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就系統面而言, 拉高ADC的AVDD看看有沒有救, (ADC PAD_VDD反而要調低, 除了降EMI外也可拉低系統noise floor).

# D" ?1 Y. ^" M! i8 q$ |! ?( s[ 本帖最後由 DennyT 於 2007-11-12 10:29 PM 編輯 ]

jeffsky

I am really thankful to DennyT's reply, it is a reasonable and constructive explanation on this issue. I will try to pull higher supply voltage to see if it can be relieved or removed or not. Thank you very much.