在鎖相迴路中如何決定迴路頻寬K呢？

option318

　如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17

kmchen3089

回復 #1 option318 的帖子
* a( ?2 d( i* q7 T8 k, L(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
% ?  ~) N  f0 t; I  [否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
* b% P/ p4 L* o6 O' u( m0 U pll ,且亦有unstability issue
' X  f$ r6 i% n, V- n# S8 I! C(see Charge-pump phase lock loops paper by Gardner
IEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
1 O" v! B( j4 u% }) N) [(2) loop BW is related to jitter (or phase noise) ,and locking time
so you have to consider loop BW  from jitter & locking time  spec
  L& @2 l9 d9 t: N$ g9 p9 D(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
(4) In my opinion ,gain margin is not considered in pll design

jasonxilion

gain margin is not considered in pll design？
3 T3 X; |4 D. F  b8 ii don't think so.
isn't it dealt with the stability?

賴永諭

書上都有講哩...加油看看先....
7 M; u* Y' q9 e* S) E應該不難找到哩...