在鎖相迴路中如何決定迴路頻寬K呢？

option318

　如題，請問先進們，在鎖相迴路中要如何決定迴路頻寬K呢？它又和Phase margin、Gain margin有關嗎？ :f17

kmchen3089

回復 #1 option318 的帖子
. u+ Y5 M# |# S8 v, G(1) 首先 open loop gain(迴路頻寬K )must <= pfd之比較頻率之十分之一
6 e  ^( h; y  G  j8 ]! X2 H否則(指>pfd之比較頻率之十分之一)要用Z domain 去分析charge pump
: I% V4 s- Z2 J8 R9 v pll ,且亦有unstability issue
8 N/ h) e5 j9 T+ s0 p, N; P2 h(see Charge-pump phase lock loops paper by Gardner
IEEE Trans.Comm,vol Com-28,pp1849-1858,November 1980)
' A/ N" i9 c' i(2) loop BW is related to jitter (or phase noise) ,and locking time
4 y3 T3 f) H/ S, ?so you have to consider loop BW  from jitter & locking time  spec
, W4 z% C( S2 M+ R5 K$ e  S. i5 i(3)phase margin is decided by relation ship among zero freq ,loop unity gain freq , pole freq
(4) In my opinion ,gain margin is not considered in pll design

jasonxilion

gain margin is not considered in pll design？
i don't think so.
isn't it dealt with the stability?

賴永諭

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