Cortex-M0+ IP Core

sinoicboy

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                                  AR085-DA-70000-r0p0-03rel0/
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                                  AR085-DA-70000-r0p0-03rel0/doc/ARMv6-M_architecture/
4af79e0557cc9c6863c2eab0f890aaad  AR085-DA-70000-r0p0-03rel0/doc/ARMv6-M_architecture/DDI0419C_arm_architecture_v6m_reference_manual.pdf
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                                  AR085-DC-11001-r0p0-04rel0/doc/errata/
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6 y* C: Q1 |" X1 u$ U                                  AT590-BU-11001-r0p1-00rel0/
b2bb2db05b71fa9e2ecd4c2841c22f3f  AT590-BU-11001-r0p1-00rel0/Cortex-M0+_Product_Errata_Notice_v4.pdf
d305236940b52b92b81e8579435efe7e  AT590-BU-11001-r0p1-00rel0/Cortex-M0+_Software_Developers_Errata_Notice_v4.pdf
2d80706f7a099ac4a9674908c50d730e  AT590-BU-11001-r0p1-00rel0/AT590-BU-11001-r0p1-00rel0.lst
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% A0 ^- w/ r) G; [' `70404309a7929774e3bd8786e10771eb  AT590-BU-50000-r0p1-00rel0/ARM_Cortex-M0+_r0p1-30rel0_ReleaseNote.pdf
                                  AT590-BU-50000-r0p1-00rel0/logical/
                                  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/
                                  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/
80fe9cfaeb5e260f70aebfcac0bdf888  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_cdc.v
063cdb1c994aca1f31971a3d52da426d  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp_sw_defs.v
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bb3812a6b967f1ffaa604a858064f1d6  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_top.v
2b71a63c5d6843c6a0c64972ca0a3483  AT590-BU-50000-r0p1-00rel0/logical/cm0p_dap/verilog/cm0p_dap_dp.v
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c00549e61aae47696609028230712dd6  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_dbg_ctl.v
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4b054567197e5f54d3bacf492271f4c9  AT590-BU-50000-r0p1-00rel0/logical/cortexm0plus/verilog/cm0p_matrix.v
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114142500

thanks! do you have source codes for M0? It‘s very great for sharing the code。my e-mail is 114142500@qq.com,thank you very much!