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Analog / Mixed Signal Examples- I+ g9 ~4 t; Z) D
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Behavioral Models of ADCs
' A9 Q9 y% @/ M. X' g- J\ams\sampling\; sampling_101;
\* r/ i3 w9 l. H, Y- @8 {3 f Sigma-Delta ADC 1st order modulator $ cd \ams\adc\; dspsdadc2;
: w* `$ `- t1 K7 V/ D Sigma-Delta ADC 2nd order modulator $ cd \ams\adc\; dspsdadc3; 3 K: ?* I6 V G' e+ D' S8 [
Sigma-Delta ADC 2nd order modulator discrete time (switched capacitor prototype) $ cd \ams\adc\; dspsdadc4; ! A4 W( z" H4 x' D. n( Z
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Behavioral RF9 q+ z- }& e, m$ V! ^' p* y! Z1 ^8 r
Measurement of Lowpass Filter Freq Response $ cd feed_fwd_2;
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PLLs
2 G, ~' C, t# e# A0 I( H VCO with phase noise $ cd
. {6 T: M: E+ o& p4 O" c B$ r Pll with freq domain instruments $ cd \ams\pll;
+ J- N9 g/ `( P) N% L Pll fractional with analog compensation $ cd \ams\pll;
Y* r$ d i/ Y; L! T0 m$ A Pll fractional with digital compensation $ cd \ams\pll;
: U" h% w- H- C) ~& z Pll optimization (Nonlinear Control Design) $ cd \ams\pll; + |! V* I$ F6 ~; q8 o! M
Carrier and Symbol Timing Recovery (NCO->ADC) $ cd \ams\pll; carrier_timing; ' W2 G. q5 i _, G7 L/ Y) p0 d
Carrier and Symbol Timing Recovery (Fractional Delay) $ cd \ams\pll; timing_recovery_1; |
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