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【工作內容】
5 H' E2 z5 n% p% P" c先進製程與模組開發 (DRAM/ Flash/ Logic)
) P% E% o% \# r/ d. v0 t- Photolithography (e-beam, EUV, OPC/RET, Photo Resist Materials),
4 k- L u9 \3 e! X8 f Dry Etch, Cleaning & CMP, Diffusion, Ion Implantation, Metallization,
. ]3 W$ c# O" e3 N3 X1 L: q Metrology & Inspection, etc.
" X1 e" R# |5 |* K- Device Isolation, Transistor, Capacitor, Dielectric
3 _- @9 X' @4 ?" X8 Y2 S* T/ n, q7 k- High-K/Metal Gate, SiO2/SiON Gate Dielectric" l+ o0 r1 x) b
- Low-K, Interconnect, etc., _! G4 [' _$ o" H5 g& C1 P& J% c
※ OPC: Optical Proximity Correction (Comput. Litho)
7 I/ s9 a, }( o& K MPC: Mask Process Correction: z( @, i( m( P+ }
: n3 z: V# W; e+ }4 f) l7 S; gFEOL/BEOL 製程整合 (DRAM/ Flash/ Logic)8 u) {7 _) i- i- R. z n% d; S( T5 ?' R
新型記憶體: PRAM, STT-MRAM, ReRAM# _4 q9 p; I, S( b: V" `2 [: C8 I' {
TCAD/ECAD3 d. U: C( ]$ P' Z% F
- Process & Device/Material Modeling, Circuit Compact/Reliability Modeling
, f9 H, N! X& q9 Y% G- Circuit Simulator Development
' t' n' d) G: K9 P' d. n- System-Level Modeling/Simulation, Virtual Platform, HW/SW Co-Design
_" K: U! Z, u/ ~0 P* A- Simics/CoWare/SOC Designer UserMemory Controller/Memory Architecture/
- F$ l- z2 u4 L- A SSD Research Experience |
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