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AMD Geode LX 800@0.9W處理器
General Features; S6 ^( g' L) @8 d' [
■ Functional blocks include:/ r- B% d' U) d4 w- s& N. K
— CPU Core# S, X7 w4 d( b
— GeodeLink™ Control Processor
3 q$ U3 Q B" U— GeodeLink Interface Units a2 R. B; M9 T- `& U; ]/ ?; k4 J
— GeodeLink Memory Controller
+ ]+ p0 J8 y! P. l h7 w/ t& O3 W; [— Graphics Processor6 h0 j. E0 g% F `& I* Q, P
— Display Controller
. K5 ~5 L' O( Q' b3 j" {5 ?— Video Processor$ i* ^/ Z% o @1 n9 {6 Y% D+ L# `
– TFT Controller/Video Output Port1 x' E& E2 s0 P. b& y, u' K
— Video Input Port; r5 t& e' t+ X4 b; V
— GeodeLink PCI Bridge' ]6 a- K, V1 j1 V
— Security Block" {$ ]0 F" d$ r% ~) v) `! [
■ 0.13 micron process/ J% G, k' ]% v& R! @0 H
■ Packaging:
5 N1 K8 {& ?: |— 481-Terminal BGU (Ball Grid Array Cavity Up) with V' y1 P+ c: {' m
internal heatspreader
5 `- e2 Q7 |1 ?4 d' v4 a, `■ Single packaging option supports all features
2 H$ N4 y5 k `9 H' z5 ^7 E6 O0 jCPU Processor Features) |8 y' L. c M2 x: [
■ x86/x87-compatible CPU core4 Q' C3 ~7 D8 E" g. D9 Q3 B, Y& j1 L/ a. {
■ Performance:1 Y0 U$ r" L {, H2 d; J# I# c6 }
— Processor frequency: up to 500 MHz; {, a9 Q/ ^$ D0 M
— Dhrystone 2.1 MIPs: 150 to 450
6 D2 s/ j6 c& N- g) E7 W— Fully pipelined FPU
3 }# p" X7 v+ _/ i3 D* J! {" X■ Split I/D cache/TLB (Translation Look-aside Buffer):, X1 S6 I( P( j" y/ M3 O" c) l
— 64 KB I-cache/64 KB D-cache
$ P8 f) m( n: B5 h% Q2 [+ Y8 G— 128 KB L2 cache configurable as I-cache, D-cache,
' x( D5 z, i1 Uor both
3 s5 }; h' j7 t* C■ Efficient prefetch and branch prediction) p5 Z3 ?8 \; m; E# z, k
■ Integrated FPU that supports the MMX® and
3 ~" T- }1 n+ T. J; `$ [: pAMD 3DNow!™ instruction sets
0 z& _$ g' r( V2 V6 n2 t, q■ Fully pipelined single precision FPU hardware with) z5 i, {; C# f( M3 y( ?9 b% B
microcode support for higher precisions
5 F% i: g; Q9 j; J8 |( ?GeodeLink™ Control Processor3 j* q) n T7 J
■ JTAG interface:
% N. A( E; X. N0 e— ATPG, Full Scan, BIST on all arrays8 I8 L1 z! H7 O7 C( [$ N% \( Z
— 1149.1 Boundary Scan compliant
5 O! d b; f# L- ?. A- H% z$ I■ ICE (in-circuit emulator) interface
. q% u+ [+ F* X% w/ W0 u0 h( b2 M■ Reset and clock control! Y. i: Z8 V* o, G- p( X
■ Designed for improved software debug methods and! V% V2 P( |4 R1 t
performance analysis
% D0 m: _& d& J6 [) `, }( C+ e■ Power Management:( m0 u! q" \; c* s" y' c
— Total Dissipated Power (TDP) 3.8W, 1.6W typical @8 \9 O- N4 i- c; ~- l
500 MHz max power, K9 [2 u& h: F% \
— GeodeLink active hardware power management: v4 @8 K( c$ M/ a7 V
— Hardware support for standard ACPI software power
! K- E- n+ g8 h: l0 imanagement- v( g# P& l) t! N! ?! F& O
— I/O companion SUSP/SUSPA power controls
' E0 `/ t0 G7 Z3 z* y% M— Lower power I/O. \+ n+ e( j2 w- D. W9 E
— Wakeup on SMI/INTR
9 h$ @, p5 M. G, `■ Designed to work in conjunction with the
/ W+ t0 }: ~; f) y8 P6 b7 ^AMD Geode™ CS5536 companion device
& ]9 b# s2 p3 L7 e8 ]GeodeLink™ Architecture
5 n/ {2 x" t/ h. Y■ High bandwidth packetized uni-directional bus for6 L! |& \) P! A( s/ U
internal peripherals/ g; R) l# Y y* V7 [' u
■ Standardized protocol to allow variants of products to be( \" U v( D8 d7 z4 ~$ [: W
developed by adding or removing modules
* P7 C" o: q! T& I9 l■ GeodeLink Control Processor (GLCP) for diagnostics
H. ]: s! c$ l* E' A& h. _+ a" rand scan control' W- T4 q- G/ L
■ Dual GeodeLink Interface Units (GLIUs) for device interconnect0 c$ V5 V7 }% u) R7 A6 `$ U
GeodeLink™ Memory Controller# e# m5 W4 E. }
■ Integrated memory controller for low latency to CPU and$ p) X! r% y9 p( x* \% X
on-chip peripherals
( s4 Q. S% g0 ~! P: z+ \& V' [/ e■ 64-bit wide DDR SDRAM bus operating frequency:
2 U) M/ X8 U; A) W: B) ~0 w0 h— 200 MHz, 400 MT/S
+ M+ `: m% V% j9 m# |6 t& [■ Supports unbuffered DDR DIMMS using up to 1 GB+ K' t7 `7 w% M* Q \, q9 c
DRAM technology
, ^8 D. q# |* C1 ?9 H■ Supports up to 2 DIMMS (16 devices max)! {, w4 }) B( ?
2D Graphics Processor
" \- F% x3 ?* z" {! T■ High performance 2D graphics controller) S" C% Y2 w6 w* r8 X/ e1 ^
■ Alpha BLT
$ c6 j- Y, B+ W4 [* g5 o$ `1 V) a■ Microsoft® Windows® GDI GUI acceleration:* z6 X. Y+ Z* G+ ^* j; ]
— Hardware support for all Microsoft RDP codes
6 [! M/ u0 f# z* | I0 f■ Command buffer interface for asynchronous BLTs
9 Z! p7 y$ h% n■ Second pattern channel support- j4 i3 O7 P. O: f g6 [% ]3 n
■ Hardware screen rotation |
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