關於undersampling ADC的問題

jeffsky

設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

jeffsky

原帖由 jeffsky 於 2007-11-8 02:07 PM 發表
設計的undersampling ADC用54MHz sample rate採樣44MHz signal，出現17MHz的雑訊，請問各位先進可否指點？
5 L" @4 G; d! j! G. C或者能否提供相關資料？因爲之前曾經看到過類似的解釋現在急需卻找不到了。：（

& H. [* n; r% N8 F3 n4 z？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？？/
- O4 M4 r2 }* J! x7 H

DennyT

17MHz 的 tone 會不會是系統OSC or XTAL 的 16.667MHz clock feedthrough noise?
. k# d6 }% I0 v
因為即使是under sampling, alias image in first order term: (FS=54MHz, Ft=44MHz, Nyquist band=27MHz)
FS-Ft=54-44=10MHz
FS+Ft=54+44=98MHz (folding 回 Nyquist band=10MHz)
& T4 K  m. X5 K: C8 {
2nd order term:
2FS-Ft=108-44=64MHz (folding 回 Nyquist band=10MHz)
2FS+Ft=108+44=152MHz (folding 回 Nyquist band=10MHz)
|FS-2Ft|=54-88=34MHz (folding 回 Nyquist band=20MHz)
FS+2Ft=54+88=142MHz (folding 回 Nyquist band=20MHz)
5 G/ X% q6 A4 _; A9 D* U: e0 s( B
- ^9 P; |( D, q8 @2nd~7th Harmonic:
5 f. E' N7 t( X4 v2nd = 20MHz
# Q/ I6 Q4 i7 I% q! O3rd = 30MHz  (folding 回 Nyquist band=24MHz)
4th = 40MHz  (folding 回 Nyquist band=14MHz)
5th = 50MHz  (folding 回 Nyquist band=4MHz)
6th = 60MHz  (folding 回 Nyquist band=6MHz)
7th = 70MHz  (folding 回 Nyquist band=16MHz)
. v) n9 X' E& R4 ^2 V! A你附的Frequency domain plot 在6th之後已在noise floor之下了, 故之後的harmonic可略去不計,
3 a/ G$ y- ~- Q但是就是沒有17MHz的theoretical noise source.
9 s' ~% L( F% o來個Maxim AN928 anti-aliasing filter的文件:

% g! ?" @0 a9 `& N[ 本帖最後由 DennyT 於 2007-11-10 12:00 AM 編輯 ]

jeffsky

Thank you for your kind reply.
5 E) N0 T' T9 RI have ever seen a paper or something else to say that when the signal frequency approaches the sample rate, the beat frequency is easy to appear at Fsig-Fs/2, for example, this frequency is 17MHz. It is as if sampling frequency is 27MHz. It is really a puzzle.

DennyT

有此一說:
  k4 W! m4 q- z4 J# O8 L# U當Fin接近於Fs/2時, ADC sample的電壓slew at full scale, 此時奇數點之間的壓差其實很小 (偶數點亦同), 但是相鄰兩點間的壓差卻很大, 測試上又稱為ADC envelope test, 而在此測試中被引進來的 "beat frequency" 會被視為noise, 使SNR下降.
+ y) P; J' I6 u$ B0 {7 b' u+ d
" }0 |2 E' L5 v0 {: D$ n% \也就是說, 若ADC內front end的PGA or buffer Amp slew rate不足, 此缺陷便很容易在此測試中被突顯出來.

就系統面而言, 拉高ADC的AVDD看看有沒有救, (ADC PAD_VDD反而要調低, 除了降EMI外也可拉低系統noise floor).
! |" @3 N: f, a# q& k
[ 本帖最後由 DennyT 於 2007-11-12 10:29 PM 編輯 ]

jeffsky

I am really thankful to DennyT's reply, it is a reasonable and constructive explanation on this issue. I will try to pull higher supply voltage to see if it can be relieved or removed or not. Thank you very much.