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Job Title :Analog Design Engineer
3 S( [; p% S0 @6 M! SJob Category :Semiconductor
% ^4 S0 y- S QLocation : Malaysia' W4 `$ N) J6 V4 ~0 S. n
Job Type : Permanent
' N* P0 R4 Y) wJob Description:
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Analog IC Designer to for all technical aspects of design from feasibility to specification to monitoring layout of the design, tapeout and silicon validation.
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Responsibilities:" K7 }: P3 |& E) S/ y
Interaction with customer to understand customer requirements, develop product specification and to provide technical support.: J$ t. ]4 q7 k% a# ^$ n6 a
Close interaction with the design team.) L# l; p/ A1 m, J
Support and guide the layout team. Proper documentation will have to be provided throughout including a detailed test plan for the validation of the design/IP.
+ ?( _8 n& b4 y6 }" w$ ?; W# B$ tMaintain proper documentation throughout projects including a detailed test plan for the validation of the design/IP.. R& x" i4 t' r& ^/ g
Requirements:
+ a* M5 H# z$ k$ c4 p$ ZIn-depth understanding of leading process technologies such as sub-micron CMOS/BiCMOS/DMOS, BCD, HV/ c% c7 x1 e9 h+ f" Y
Experience with simulation tools required to efficiently simulate analog/mixed-signal circuits e.g. Spectre, Ultrasim, HSpice etc/ E# y# n5 d+ D
Understanding of simulation models, design rules and verification procedures (DRC/LVS/ERC) is essential.# v2 Z9 D8 p! I6 y2 z; m* V0 e
Detailed knowledge in the design and operation of the following analog blocks:
$ p) T. Z& ]- P( Q- Basic analog building blocks (op amps, comparators, current sources, current mirrors, voltage references)) |' \: {) N& x7 y" `: @2 B
- Power management blocks (bandgap references, linear regulators, DC-DC converter of various topologies, LDOs). X$ O; F' o6 ?
- System level protection blocks (UVLO, POR, OTP, Short circuit protection etc)
8 Q8 ]: P* ?5 Z" F) c" H- PLL and transceiver blocks (output drivers, multiplexer and de-multiplexer, clock generator, equalizers, clock and data recovery, frequency detectors, oscillators, filters)
4 m* f% b/ ~- ?0 X- ADCs and DACs: @3 ~5 L& F: T6 S
Experience with design practices such as minimizing device mismatch, noise, signal coupling, ESD, latchup and device SOA is a must.
- ~6 u* E) B, zModelling and design skills in Verilog-A/Verilog-AMS and system modelling with Matlab is an added advantage.
( M: G- o7 ~$ G& s3 v) c; o0 lA track record as a team player and capable of leading teams
8 {3 N* M) i9 B$ x2 VProven experience in developing and meeting engineering schedules
8 g T5 K9 h* `Strong analytical skills" C) B( M2 V8 T7 k4 i2 ?. V2 e
Strong organizational, interpersonal, written and verbal communication skills. |
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