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Job Title :Analog Design Engineer
7 I8 D0 K; m6 T# AJob Category :Semiconductor
# o9 _; j9 |$ `6 N0 P5 e+ SLocation : Malaysia
" j& B& K3 o% f1 `, |2 sJob Type : Permanent
$ i; X: l# d3 `1 a) X( T. \0 ^Job Description:
! j3 R( Q( J- b" @5 s+ [0 k( d- {
8 L# Y' X) k1 v/ \, HAnalog IC Designer to for all technical aspects of design from feasibility to specification to monitoring layout of the design, tapeout and silicon validation., x4 ~( ^9 Q2 x8 v/ {& t
7 Z+ k: h+ y9 a5 j1 KResponsibilities: m1 n7 d* @$ w, w' N
Interaction with customer to understand customer requirements, develop product specification and to provide technical support.1 V L' B) Q/ i* v
Close interaction with the design team.& M2 N \# Z. ]4 w; m
Support and guide the layout team. Proper documentation will have to be provided throughout including a detailed test plan for the validation of the design/IP.
( a8 e3 M: N. ]# iMaintain proper documentation throughout projects including a detailed test plan for the validation of the design/IP.$ b! ]$ W# a$ `
Requirements:
u( R- e- m2 }In-depth understanding of leading process technologies such as sub-micron CMOS/BiCMOS/DMOS, BCD, HV$ S h. }/ c0 v$ g
Experience with simulation tools required to efficiently simulate analog/mixed-signal circuits e.g. Spectre, Ultrasim, HSpice etc
5 ]; B' Q& i( O- V* \6 lUnderstanding of simulation models, design rules and verification procedures (DRC/LVS/ERC) is essential.
' n. I( t. _# p. ]9 Z; n' {% \4 nDetailed knowledge in the design and operation of the following analog blocks:
' Z+ i' o z( m6 [- ~9 C! L9 |- Basic analog building blocks (op amps, comparators, current sources, current mirrors, voltage references)
7 i4 i: p* | `! l- Power management blocks (bandgap references, linear regulators, DC-DC converter of various topologies, LDOs) ?% }" L9 h3 S
- System level protection blocks (UVLO, POR, OTP, Short circuit protection etc)
' P6 ], D7 o5 I4 D8 _. P- PLL and transceiver blocks (output drivers, multiplexer and de-multiplexer, clock generator, equalizers, clock and data recovery, frequency detectors, oscillators, filters)' I+ x$ r( Y5 k# R( ~$ k
- ADCs and DACs
?2 p+ v5 n- ^4 nExperience with design practices such as minimizing device mismatch, noise, signal coupling, ESD, latchup and device SOA is a must.
- L+ q; `' Z& K" t" D! p: N$ ~Modelling and design skills in Verilog-A/Verilog-AMS and system modelling with Matlab is an added advantage.2 W5 w8 B( P) s4 C/ t
A track record as a team player and capable of leading teams
5 R9 g4 n) S" E2 W; }% _, `" JProven experience in developing and meeting engineering schedules; _+ Q7 j# L9 A" }7 M
Strong analytical skills) _3 s8 r2 d$ D
Strong organizational, interpersonal, written and verbal communication skills. |
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